CLC030 datasheet(6/29 Pages) NSC

6 / 29 page

DC Electrical Characteristics (Continued)

Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Notes 2, 3).

Symbol

Parameter

Conditions

Reference

Min

Typ

Max

Units

(2.5V)

Power Supply Current,

2.5V Supply, Total

CLK = 27 MHz, NTSC

Colour Bar Pattern, Test

Circuit, Test Loads Shall

Apply

DDD,VDDZ,

DDPLL

(2.5V)

Power Supply Current,

2.5V Supply, Total

CLK = 74.25 MHz, NTSC

Colour Bar Pattern, Test

Circuit, Test Loads Shall

Apply

DDD,VDDZ,

DDPLL

110

AC Electrical Characteristics

Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Note 3).

Symbol

Parameter

Conditions

Reference

Min

Typ

Max

Units

VCLK

Parallel Video Clock

Frequency

CLK

74.25

MHz

Video Clock Duty

Cycle

CLK

ACLK

Ancilliary Clock

Frequency

CLK

MHz

Ancilliary Clock Duty

Cycle

CLK

r,tf

Input Clock and Data

Rise Time, Fall Time

10%–90%

CLK,ACLK,

N,ADN

1.0

1.5

3.0

SDO

Serial Data Rate

(Notes 5, 6)

SDO, SDO

270

1,485

bps

r,tf

Rise Time, Fall Time

20%–80%, (Note 6)

SDO, SDO

270

r,tf

Rise Time, Fall Time

20%–80%, (Note 5)

SDO, SDO

500

Output Overshoot

(Note 4)

SDO, SDO

Serial Output Jitter,

Intrinsic

270 M

bps, (Notes 5, 9, 10)

SDO, SDO

200

P-P

Serial Output Jitter,

Intrinsic

1,485 M

bps, (Notes 6, 9, 10)

SDO, SDO

120

P-P

LOCK

Lock Time

(Notes 5, 7) (SD Rates)

LOCK

Lock Time

(Notes 6, 7) (HD Rates)

Setup Time, Video

Data

Timing Diagram, (Note 4)

N to VCLK

1.5

2.0

Hold Time, Video

Data

Timing Diagram, (Note 4)

CLK to DVN

1.5

2.0

Setup Time, Anc.

Data Port

Timing Diagram, (Note 4)

N to ACLK

1.5

2.0

Hold Time, Anc. Data

Port

Timing Diagram, (Note 4)

CLK to ADN

1.5

2.0

Note 1: “Absolute Maximum Ratings” are those parameter values beyond which the life and operation of the device cannot be guaranteed. The stating herein of

these maximums shall not be construed to imply that the device can or should be operated at or beyond these values. The table of “Electrical Characteristics”

specifies acceptable device operating conditions.

Note 2: Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are referenced to VSS =0V.

Note 3: Typical values are stated for VDDIO =VDDSD = +3.3V, VDDD =VDDPLL = +2.5V and TA = +25˚C.

Note 4: Spec. is guaranteed by design.

Note 5: RL =75Ω, AC-coupled @ 270 Mbps,RREFLVL = RREFPRE = 4.75 kΩ 1%, See Test Loads and Test Circuit.

Note 6: RL =75Ω, AC-coupled @ 1,485 Mbps,RREFLVL = RREFPRE = 4.75 kΩ 1%, See Test Loads and Test Circuit.

Note 7: Measured from rising-edge of first DVCLK cycle until Lock Detect output goes high (true). Lock time includes format detection time plus PLL lock time.

Note 8: Average value measured between rising edges computed over at least one video field.

Note 9: Intrinsic timing jitter is measured in accordance with SMPTE RP 184-1996, SMPTE RP 192-1996 and the applicable serial data transmission standard,

SMPTE 259M-1997 or SMPTE 292M (proposed). A colour bar test pattern is used. The value of fSCLK is 270 MHz or 360 MHz for SMPTE 259M, 540MHz for SMPTE

344M or 1,485 MHz for SMPTE 292M serial data rates. See Timing Jitter Bandpass section.

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