CLC030 datasheet(10/29 Pages) NSC

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Device Operation (Continued)

pendent of the video data clock, VCLK. Inputs AD[9:0],

RD/WR and ANC/CTRL have internal pull down devices.

ACLK does not have an internal pull down device.

Control Data Read Functions

Control data is input to and output from the CLC030 using

the lower-order 8 bits AD[7:0] of the Ancilliary/Control Data

Port. This control data initializes, monitors and controls op-

eration of the CLC030. The upper two bits AD[9:8] of the

port function as handshaking signals with the device access-

ing the port. AD[9:8] must be driven as 00b (0XXh, where

XX are AD[7:0]) when either a control register read or write

address is being written to the port. AD[9:8] must be driven

as 11b (3XXh, where XX are AD[7:0]) when control data is

being written to the port. When control data is being read

from the port, the CLC030 will output AD[9:8] as 10b (2XXh,

where XX are output data AD[7:0]) and may be ignored by

the monitoring system.

Note: When power is first applied to the device or after it is

reset, the Ancilliary and Control Data Port must be initial-

ized to receive data. This is done by toggling ACLK three (3)

times.

Figure 1 shows the sequence of clock and control signals for

reading control data from the ancilliary/control data port.

Control data read mode is invoked by making the

ANC/CTRL input low and the RD/WR input high. The 8-bit

address of the control register set to be accessed is input to

the port on bits AD[7:0]. The address is captured on the

rising edge of ACLK. When a control register read address

is being written to the port, AD[9:8] must be driven as 00b

(0XXh, where XX are AD[7:0]). When control data is being

read from the port, the CLC030 will output AD[9:8] as 10b

(2XXh, where XX are output data AD[7:0]) and may be

ignored by the monitoring system. Data being output from

the selected register is driven by the port immediately follow-

ing the rising edge of ACLK or when the address signals are

removed. For optimum system timing, the address signals

driving the port should be removed immediately after the

address is clocked into the device and before or coincident

with the falling edge of ACLK at the end of the address

cycle. Output data remains stable until the next rising edge

of ACLK and may be read by external devices at any time

after the removal of the address signal. This second clock

resets the port from drive to receive mode and readies the

port for another access cycle.

Example: Read the Full-field Flags via the AD port.

Set ANC/CTRL to a logic-low.

Set RD/WR to a logic-high.

Present 001h to AD[9:0] as the register address.

Toggle ACLK.

Release the bus driving the AD port.

Read the data present on the AD port. The Full-field

Flags are bits AD[4:0].

Toggle ACLK to release the AD port.

Control Data Write Functions

Figure 2 shows the sequence of clock and control signals for

writing control data to the ancilliary/control data port. The

control data write mode is similar to the read mode. Con-

trol data write mode is invoked by making the ANC/CTRL

input low and the RD/WR input low. The 8-bit address of the

control register set to be accessed is input to the port on bits

AD[7:0]. The address is captured on the rising edge of

ACLK. The address data is removed after being clocked into

the device or before the falling edge of ACLK. Next, the

control data is presented to the port bits AD[7:0] and written

into the selected register on the next rising edge of ACLK.

When a control register write address is being written to the

port, AD[9:8] must be driven as 00b (0XXh, where XX are

AD[7:0]). When control data is being written to the port,

AD[9:8] must be driven as 11b (3XXh, where XX are

AD[7:0]). Control data written into the registers may be read

out non-destructively in most cases.

Example: Setup (without enabling) the TPG Mode via the

AD port using the 1125 line, 30 frame, 74.25MHz, interlaced

component (SMPTE 274M) colour bars as test pattern. The

TPG may be enabled after setup using the Multi-function I/O

port or by the control registers.

Set ANC/CTRL to a logic-low.

Set RD/WR to a logic-low.

Present 00Dh to AD[9:0] as the Test 0 register address.

Toggle ACLK.

Present 027h to AD[9:0] as the register data.

Toggle ACLK.

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