CLC030 datasheet(11/29 Pages) NSC

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Device Operation (Continued)

Ancilliary Data Functions

The CLC030 can insert Ancilliary Data into the serial data

stream. This ancilliary data and related control characters

are defined in the relevant SMPTE standards and may re-

side in the horizontal and vertical blanking intervals. The

data can consist of different types of message packets in-

cluding audio data. The serial ancilliary data space must be

formatted according to SMPTE 291M. The CLC030 supports

ancilliary data in the chrominance channel (C’r/C’b) only for

high-definition operation. Ancilliary data for standard defini-

tion follows the requirements of SMPTE 125M.

Figure 3 shows the sequence of clock, data and control

signals for writing ancilliary data to the port. In ancilliary data

write mode, 10-bit Ancilliary Data is written into the port

using bits AD[9:0] and routed to the ancilliary data FIFO.

From the FIFO, the ancilliary data can be written into the

ancilliary data spaces in the serial video data stream. Ancil-

liary data write mode is invoked by making the ANC/CTRL

input high and the RD/WR input low. Data presented to the

port on a falling edge of ACLK is written into the FIFO on the

next rising edge of ACLK. Ancilliary data may only be written

to the FIFO when in the ancilliary data mode. Ancilliary data

cannot be read from the port.

Admission of ancilliary data to and insertion into the video

data stream from the FIFO is controlled by a system of

masking and control bits in the control registers. The details

and functions of these control registers and bits is explained

later in this datasheet.

DS200003-9

FIGURE 1. Control Data Read Timing (2 read and 1 write cycle shown)

DS200003-10

FIGURE 2. Control Data Write Timing

CLC030 数据表(PDF) 11 Page - National Semiconductor (TI)