CLC030 datasheet(12/29 Pages) NSC

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Device Operation (Continued)

MULTI-FUNCTION I/O PORT

The multi-function I/O port can be configured to provide

immediate access to many control and indicator functions

within the CLC030 configuration and control registers. The

individual pins comprising this port are assigned as input or

output for selected bits in the control data registers. The

multi-function I/O port is configured by way of an 8x6-bit

CONFIG through I/O pin 7 CONFIG. The contents of these

registers determine whether the port bits function as inputs

or outputs and to which register element each port bit is

assigned. Port bits may be assigned to access different

access the same register element (an unlikely or unusual

situation). Controls and indicators that are accessible by the

port and their corresponding selection addresses are given

in the I/O Pin Configuration Register Addresses,

Table 6.

Table 2 gives the control register bit assignments.

Caution: When writing data into the control registers via the

multi-function I/O port, ACLK must be toggled to register the

data as shown in

Figure 4. It is not necessary to toggle

ACLK when reading data from the multi-function I/O port.

Example: Program multi-function I/O port bit-0 as the CRC

Luma Error bit output.

Set ANC/CTRL to a logic-low.

Set RD/WR to a logic-low.

Present 00Fh to AD[9:0] as the I/O PIN 0 CONFIG

Toggle ACLK.

Present 310h to AD[9:0] as the register data.

Toggle ACLK.

EDH/CRC SYSTEM

The CLC030 has EDH and CRC character generation and

insertion circuitry. The EDH system functions as described

in SMPTE Recommended Practice RP-165. The CRC sys-

tem functions as specified in SMPTE 292M. The EDH/CRC

polynomial generators accept parallel data from the input

insertion in the serial data. Incoming parallel data is checked

for errors and the EDH flags are updated automatically. EDH

check words and status flags for SDTV data are generated

using the polynomial X

16 +X12 +X6 + 1 per SMPTE RP165.

EDH check words are inserted in the serial data stream at

the correct positions in the ancilliary data space and format-

ted per SMPTE 291M. Generation and automatic insertion of

the EDH check words is controlled by EDH Force and EDH

Enable bits in the control registers. After a reset, the initial

state of all EDH and CRC check characters is 00h.

The SMPTE 292M high definition video standard employs

CRC (cyclic redundancy check codes) error checking in-

stead of EDH. The CRC consists of two 18-bit words gener-

ated using the polynomial X

18 +X5 +X4 + 1 per SMPTE

292M. One CRC is used for luminance and one for chromi-

nance data. CRC data is inserted at the required place in the

video data according to SMPTE 292M. The CRCs appear in

the data stream following the EAV and line number charac-

ters.

EDH and CRC errors are reported in the EDH0, EDH1, and

EDH2 register sets of the configuration and control registers.

PHASE-LOCKED LOOP SYSTEM

The phase-locked loop (PLL) system generates the output

serial data clock at 10x (standard definition) or 20x (high

definition) the parallel data clock frequency. This system

consists of a VCO, divider chain, phase-frequency detector

and internal loop filter. The VCO free-running frequency is

internally set. The PLL automatically generates the appropri-

ate frequency for the serial clock rate using the parallel data

clock (VCLK) frequency as its reference. Loop filtering is

internal to the CLC030. The VCO has separate analog and

digital power supply feeds: V

DDPLLA pin 62, VSSPLLA pin 61,

DDPLLD pin 1, and VSSPLLD pin 2. These may be separately

supplied power via external low-pass filters, if desired. PLL

acquisition time is less than 200µs @ 1,485 Mbps. The VCO

halts when VCLK signal is not present or is inactive.

A LOCK DETECT indicator function is available as a bit in

the VIDEO INFO 0 control registers. LOCK DETECT is a

logic-1 when the PLL is locked and can be assigned as an

output on the multifunction I/O port. The power-on or reset

default assigns LOCK DETECT as I/O Port bit 4. This func-

tion also includes logic to check the stability of the device

after the digital logic reset is released following PLL lock. If

the system is not fully stable, the logic is automatically reset.

LOCK DETECT also combines the function of indicating that

DS200003-11

FIGURE 3. Ancilliary Data Write Timing

DS200003-12

FIGURE 4. I/O Port Data Write Timing

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