CLC030 datasheet(18/29 Pages) NSC

18 / 29 page

Device Operation (Continued)

TABLE 3. Control Register Addresses

Address

Decimal

Address

Hexadecimal

EDH 0

EDH 1

EDH 2

ANC 0

ANC 1

ANC 2

ANC 3

ANC 4

ANC 5

ANC 6

SWITCH POINT 0

SWITCH POINT 1

SWITCH POINT 2

SWITCH POINT 3

FORMAT 0

FORMAT 1

TEST 0

VIDEO INFO 0

I/O PIN 0 CONFIG

I/O PIN 1 CONFIG

I/O PIN 2 CONFIG

I/O PIN 3 CONFIG

I/O PIN 4 CONFIG

I/O PIN 5 CONFIG

I/O PIN 6 CONFIG

I/O PIN 7 CONFIG

TEST MODE 0

EDH REGISTERS 0, 1 AND 2 (Addresses 01h through

03h)

The CRC Error flag indicates that parallel data has been

input that contains detected errors in either the EDH check-

sums (SD) or CRC checkwords (HD).

Updated EDH packets may be inserted into the serial output

data by setting the EDH Force bit in the control registers.

The EDH Force control bit causes the insertion of new EDH

checkwords and flags into the serial output regardless of the

previous condition of EDH checkwords and flags in the input

parallel data. This function may be used in situations where

video content has been editted thus making the previous

EDH information invalid. In the case of SMPTE 292M data,

the CRC check characters are recalculated and inserted

automatically regardless of the presence of CRC characters

in the parallel data. After the CLC030 is reset, the initial state

of the CRC check characters is 00h.

The EDH Enable bit enables operation of the EDH generator

function.

The EDH flags F/F FLAGS[4:0] (full field), A/P FLAGS[4:0]

(active picture) and ANC FLAGS[4:0] (ancilliary data) are

defined in SMPTE RP 165. The EDH flags are stored in the

control registers. The flags are updated automatically when

the EDH function is enabled and data is being received.

The status of EDH flag errors in incoming SD parallel data

are reported in the ffFlagError, apFlagError and anc-

FlagError bits. The ffFlagError, apFlagError and anc-

FlagError bits are the logical-OR of the corresponding EDH

and EDA flags of the EDH checkwords.

CRC errors in incoming HD parallel data are reported in the

CRC ERROR, CRC ERROR LUMA and CRC ERROR

CHROMA bits in the control registers.

ANC REGISTERS 1 THROUGH 6 (Addresses 04h

through 08h, 17h and 18h)

The V FIFO Depth[2:0] bits control the depth of the video

FIFO which follows the input data latches. The depth can be

set from 0 to 4 stages deep by writing the corresponding

binary code into these bits. For example: to set the Video

FIFO depth at two registers, load 11010XXXXXb into the

ANC 0 control register (where X represents the other func-

tional bits of this register). To retain other data previously

stored in a register, read the register’s contents and

logically-OR this with the new data. Then write the compos-

ite data back into the register.

Flags for FIFO EMPTY, FIFO FULL and FIFO OVERRUN

are available in the configuration and control register set.

These flags can also be assigned as inputs and outputs on

the multi-function I/O port. The FIFO OVERRUN flag indi-

cates that an attempt to write data into a full FIFO has

occurred. When FIFO FLUSH DYNAMIC or MSG FLUSH

DYNAMIC are enabled, the FIFO OVERRUN function is

superceded. When FIFO OVERRUN is active and not super-

ceded, it can be reset by reading the bit’s status via the

Ancilliary/Command port. To be used properly, FIFO OVER-

RUN should be assigned as an output on the multi-function

I/O port and monitored by the host system. Otherwise, inad-

vertent loss of ancilliary packet data could occur.

The ANC Checksum Force bit, under certain conditions,

enables the overwriting of ancilliary data checksums re-

ceived in the parallel ancilliary data. Calculation and inser-

tion of new ancilliary data checksums is controlled by the

ANC Checksum Force bit. If a checksum error is detected

(calculated and received checksums do not match) and the

ANC Checksum Force bit is set, a new checksum will be

inserted in the ancilliary data replacing the previous one. If a

checksum error is detected and the ANC Checksum Force

bit is not set, the checksum mismatch is reported via the

ANC Checksum Error bit.

Ancilliary data checksums may be received in the incom-

ing parallel ancilliary data. Alternatively they may be calcu-

lated and inserted automatically by the CLC030. The CHK-

SUM ATTACH IN bit in the control registers when set to a

logic-1 indicates that the checksum is to be supplied in the

incoming data. When the CHKSUM ATTACH IN bit is set,

checksums for incoming data are calculated and checked

against received checksums. Calculation and insertion of

new ancilliary data checksum is controlled by the ANC

Checksum Force bit in the configuration and control regis-

ters. If a checksum error is detected (calculated and re-

ceived checksums do not match) and the ANC Checksum

Force bit is set, a new checksum will be inserted in the

ancilliary data replacing the previous one. If a checksum

error is detected and the ANC Checksum Force bit is not

set, the checksum mismatch is reported via the ANC

CHECKSUM ERROR bit in the control registers.

The ANC Checksum Error bit indicates that the received

ancilliary data checksum did not agree with the CLC030’s

internally generated checksum. This bit is available as an

output on the multifunction I/O port.

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