AD9883ASLASHPCB datasheet(12/28 Pages) AD

12 / 28 page

REV. B

AD9883A

–12–

The PLL characteristics are determined by the loop filter design, by

the PLL Charge Pump Current, and by the VCO range setting.

The loop filter design is illustrated in Figure 6. Recommended

settings of VCO range and charge pump current for VESA

standard display modes are listed in Table V.

CP 0.0082 F

0.082 F CZ

2.7k

FILT

PVD

Figure 6. PLL Loop Filter Detail

Four programmable registers are provided to optimize the per-

formance of the PLL. These registers are:

1. The 12-Bit Divisor Register. The input Hsync frequencies

range from 15 kHz to 110 kHz. The PLL multiplies the

frequency of the Hsync signal, producing pixel clock

frequencies in the range of 12 MHz to 110 MHz. The

Divisor Register controls the exact multiplication factor.

This register may be set to any value between 221 and 4095.

(The divide ratio that is actually used is the programmed

divide ratio plus one.)

2. The 2-Bit VCO Range Register. To improve the noise

performance of the AD9883A, the VCO operating frequency

range is divided into three overlapping regions. The VCO

Range Register sets this operating range. The frequency

ranges for the lowest and highest regions are shown in Table II.

Table II. VCO Frequency Ranges

Pixel Clock Range (MHz)

PV1

PV0

AD9883AKST

AD9883ABST

12–32

12–30

32–64

30–60

64–110

60–120

110–140

120–140

3. The 3-Bit Charge Pump Current Register. This register

allows the current that drives the low-pass loop filter to be

varied. The possible current values are listed in Table III.

Table III. Charge Pump Current/Control Bits

Ip2

Ip1

Ip0

Current ( A)

100

150

250

350

500

750

1500

4. The 5-Bit Phase Adjust Register. The phase of the generated

sampling clock may be shifted to locate an optimum sampling

point within a clock cycle. The Phase Adjust Register provides

32 phase-shift steps of 11.25

° each. The Hsync signal with

an identical phase shift is available through the HSOUT pin.

The COAST pin is used to allow the PLL to continue to run

at the same frequency, in the absence of the incoming Hsync

signal or during disturbances in Hsync (such as equalization

pulses). This may be used during the vertical sync period, or

any other time that the Hsync signal is unavailable. The

polarity of the COAST signal may be set through the Coast

Polarity Register. Also, the polarity of the Hsync signal

may be set through the Hsync Polarity Register. If not

using automatic polarity detection, the Hsync and COAST

Polarity bits should be set to match the respective polarities

of the input signals.

Power Management

The AD9883A uses the activity detect circuits, the active inter-

face bits in the serial bus, the active interface override bits, and

the power-down bit to determine the correct power state. There

are three power states, full-power, seek mode, and power-down.

Table IV summarizes how the AD9883A determines what power

mode to be in and which circuitry is powered on/off in each of

these modes. The power-down command has priority over the

automatic circuitry.

Table IV. Power-Down Mode Descriptions

Inputs

Power-

Sync

Powered On or

Mode

Down

Detect

Comments

Full-Power

Everything

Seek Mode

Serial Bus, Sync

Activity Detect, SOG,

Band Gap Reference

Power-Down

Serial Bus, Sync

Activity Detect, SOG,

Band Gap Reference

NOTES

1Power-down is controlled via Bit 1 in serial bus register 0FH.

2Sync detect is determined by OR-ing Bits 7, 4, and 1 in serial bus register 14H.

AD9883A/PCB 数据表(PDF) 12 Page - Analog Devices

AD9883A/PCB 数据表(HTML) 12 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

数据表下载