REV. B

AD9883A

–17–

2-WIRE SERIAL CONTROL REGISTER DETAIL CHIP

IDENTIFICATION

00

7–0

Chip Revision

An 8-bit register that represents the silicon revision. Revi-

sion 0 = 0000 0000, Revision 1 = 0000 0001, Revision 2 =

0000 0010.

PLL DIVIDER CONTROL

01

7–0

PLL Divide Ratio MSBs

The 8 most significant bits of the 12-bit PLL divide ratio

PLLDIV. (The operational divide ratio is PLLDIV + 1.)

The PLL derives a master clock from an incoming Hsync

signal. The master clock frequency is then divided by an

integer value, such that the output is phase-locked to

Hsync. This PLLDIV value determines the number of

pixel times (pixels plus horizontal blanking overhead) per

line. This is typically 20% to 30% more than the number

of active pixels in the display.

The 12-bit value of the PLL divider supports divide ratios

from 2 to 4095. The higher the value loaded in this regis-

ter, the higher the resulting clock frequency with respect

to a fixed Hsync frequency.

VESA has established some standard timing specifications

that assist in determining the value for PLLDIV as a

function of horizontal and vertical display resolution and

frame rate (Table V).

However, many computer systems do not conform pre-

cisely to the recommendations, and these numbers should

be used only as a guide. The display system manufacturer

should provide automatic or manual means for optimizing

PLLDIV. An incorrectly set PLLDIV will usually produce

one or more vertical noise bars on the display. The greater

the error, the greater the number of bars produced.

The power-up default value of PLLDIV is 1693

(PLLDIVM = 69H, PLLDIVL = DxH).

The AD9883A updates the full divide ratio only when the

LSBs are changed. Writing to the MSB by itself will not

trigger an update.

02

7–4

PLL Divide Ratio LSBs

The 4 least significant bits of the 12-bit PLL divide ratio

PLLDIV. The operational divide ratio is PLLDIV + 1.

The power-up default value of PLLDIV is 1693

(PLLDIVM = 69H, PLLDIVL = DxH).

The AD9883A updates the full divide ratio only when this

register is written to.

CLOCK GENERATOR CONTROL

03

7–6

VCO Range Select

Two bits that establish the operating range of the clock

generator.

VCORNGE must be set to correspond with the desired

operating frequency (incoming pixel rate).

The PLL gives the best jitter performance at high fre-

quencies. For this reason, to output low pixel rates and

still get good jitter performance, the PLL actually operates

at a higher frequency but then divides down the clock rate

afterwards. Table VII shows the pixel rates for each VCO

range setting. The PLL output divisor is automatically

selected with the VCO range setting.

Table VII. VCO Ranges

VCORNGE

Pixel Rate Range

00

12–32

01

32–64

10

64–110

11

110–140

The power-up default value is 01.

03

5–3

CURRENT Charge Pump Current

Three bits that establish the current driving the loop filter

in the clock generator.

Table VIII. Charge Pump Currents

CURRENT

Current ( A)

000

50

001

100

010

150

011

250

100

350

101

500

110

750

111

1500

CURRENT must be set to correspond with the desired

operating frequency (incoming pixel rate).

The power-up default value is current = 001.

Table VI. Control Register Map (continued)

Write and

Hex

Read or

Default

Register

Address

Read Only

Bits

Value

Name

Function

16H

R/

W

7:0

Test Register

Reserved for future use.

17H

RO

7:0

Test Register

Reserved for future use.

18H

RO

7:0

Test Register

Reserved for future use.

*The AD9883A only updates the PLL divide ratio when the LSBs are written to (register 02H).