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AD9883A/PCB 数据表(PDF) 22 Page - Analog Devices |
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AD9883A/PCB 数据表(HTML) 22 Page - Analog Devices |
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22 / 28 page  REV. B AD9883A –22– Table XXXIV. Detected Coast Input Polarity Status Polarity Status Result 0Coast Polarity Negative 1Coast Polarity Positive This indicates that Bit 1 of Register 5 is the 4:2:2 Output mode select bit. 15 1 4:2:2 Output Mode Select A bit that configures the output data in 4:2:2 mode. This mode can be used to reduce the number of data lines used from 24 down to 16 for applications using YUV, YCbCr, or YPbPr graphics signals. A timing diagram for this mode is shown in Figure 9. Recommended input and output configurations are shown in Table XXXV. Table XXXV. 4:2:2 Output Mode Select Select Output Mode 0 4:2:2 1 4:4:4 Table XXXVI. 4:2:2 Input/Output Configuration Input Channel Connection Output Format Red V U/V Green Y Y Blue U High Impedance 2-WIRE SERIAL CONTROL PORT A 2-wire serial interface control interface is provided. Up to two AD9883A devices may be connected to the 2-wire serial interface, with each device having a unique address. The 2-wire serial interface comprises a clock (SCL) and a bidi- rectional data (SDA) pin. The analog flat panel interface acts as a slave for receiving and transmitting data over the serial interface. When the serial interface is not active, the logic levels on SCL and SDA are pulled high by external pull-up resistors. Data received or transmitted on the SDA line must be stable for the duration of the positive-going SCL pulse. Data on SDA must change only when SCL is low. If SDA changes state while SCL is high, the serial interface interprets that action as a start or stop sequence. There are five components to serial bus operation: • Start Signal • Slave Address Byte • Base Register Address Byte • Data Byte to Read or Write • Stop Signal When the serial interface is inactive (SCL and SDA are high) communications are initiated by sending a start signal. The start signal is a high-to-low transition on SDA while SCL is high. This signal alerts all slaved devices that a data transfer sequence is coming. The first eight bits of data transferred after a start signal com- prise a 7-bit slave address (the first seven bits) and a single R/ W Bit (the eighth bit). The R/ W Bit indicates the direction of data transfer, read from (1) or write to (0) the slave device. If the transmitted slave address matches the address of the device (set by the state of the SA1-0 input pins in Table XXXIV, the AD9883A acknowledges by bringing SDA low on the ninth SCL pulse. If the addresses do not match, the AD9883A does not acknowledge. Table XXXVII. Serial Port Addresses Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 A6 A5 A4 A3 A2 A1 A0 (MSB) 10 01100 10 01101 Data Transfer via Serial Interface For each byte of data read or written, the MSB is the first bit of the sequence. If the AD9883A does not acknowledge the master device during a write sequence, the SDA remains high so the master can gen- erate a stop signal. If the master device does not acknowledge the AD9883A during a read sequence, the AD9883A interprets this as “end of data.” The SDA remains high so the master can generate a stop signal. Writing data to specific control registers of the AD9883A requires that the 8-bit address of the control register of interest be written after the slave address has been established. This control register address is the base address for subsequent write operations. The base address autoincrements by one for each byte of data written after the data byte intended for the base address. If more bytes are transferred than there are available addresses, the address will not increment and remains at its maximum value of 14H. Any base address higher than 14H will not produce an acknowledge signal. SDA SCL tBUFF tSTAH tDHO tDSU tDAL tDAH tSTASU tSTOSU Figure 10. Serial Port Read/Write Timing |
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