AD9883ASLASHPCB datasheet(16/28 Pages) AD

16 / 28 page

REV. B

AD9883A

–16–

Table VI. Control Register Map (continued)

Write and

Hex

Read or

Default

Address

Read Only

Bits

Value

Name

Function

0FH

R/W

7:1

*******

Bit 7 – Clamp Function. Chooses between Hsync for Clamp

signal or another external signal to be used for clamping.

(Logic 0 = Hsync, Logic 1 = Clamp.)

*1******

Bit 6 – Clamp Polarity. Valid only with external Clamp signal.

(Logic 0 = Active High, Logic 1 Selects Active Low.)

**0*****

Bit 5 – Coast Select. Logic 0 selects the coast input pins to be

used for the PLL coast. Logic 1 selects Vsync to be used for the

PLL coast.

***0****

Bit 4 – Coast Polarity Override. (Logic 0 = Polarity determined by

chip, Logic 1 = Polarity set by Bit 3 in register 0FH.)

****1***

Bit 3 – Coast Polarity. Selects polarity of external Coast signal.

(Logic 0 = Active Low, Logic 1 = Active High.)

*****1**

Bit 2 – Seek Mode Override. (Logic 1 = Allow Low Power Mode,

Logic 0 = Disallow Low Power Mode.)

******1*

Bit 1 – PWRDN. Full Chip Power-Down, Active Low. (Logic 0 =

Full Chip Power-Down, Logic 1 = Normal.)

10H

R/W

7:3

10111

***

Sync-on-Green

Sync-on-Green Threshold. Sets the voltage level of the Sync-on-

Threshold

Green slicer’s comparator.

*****0**

Bit 2 – Red Clamp Select. Logic 0 selects clamp to ground.

Logic 1 selects clamp to midscale (voltage at Pin 37).

******0*

Bit 1 – Green Clamp Select. Logic 0 selects clamp to ground.

Logic 1 selects clamp to midscale (voltage at Pin 37).

*******0

Bit 0 – Blue Clamp Select. Logic 0 selects clamp to ground.

Logic 1 selects clamp to midscale (voltage at Pin 37).

11H

R/W

7:0

00100000

Sync Separator

Sync Separator Threshold. Sets how many internal 5 MHz clock

Threshold

periods the sync separator will count to before toggling high or low.

This should be set to some number greater than the maximum

Hsync or equalization pulsewidth.

12H

R/W

7:0

00000000

Pre-Coast

Pre-Coast. Sets the number of Hsync periods that Coast becomes

active prior to Vsync.

13H

R/W

7:0

00000000

Post-Coast

Post-Coast. Sets the number of Hsync periods that Coast stays

active following Vsync.

14H

7:0

Sync Detect

Bit 7 – Hsync detect. It is set to Logic 1 if Hsync is present on the

analog interface; otherwise it is set to Logic 0.

Bit 6 – AHS: Active Hsync. This bit indicates which analog Hsync

is being used. (Logic 0 = Hsync Input Pin, Logic 1 = Hsync from

Sync-on-Green.)

Bit 5 – Input Hsync Polarity Detect. (Logic 0 = Active Low,

Logic 1 = Active High.)

Bit 4 – Vsync Detect. It is set to Logic 1 if Vsync is present on the

analog interface; otherwise it is set to Logic 0.

Bit 3 – AVS: Active Vsync. This bit indicates which analog Vsync

is being used. (Logic 0 = Vsync Input Pin, Logic 1 = Vsync from

Sync Separator.)

Bit 2 – Output Vsync Polarity Detect. (Logic 0 = Active Low,

Logic 1 = Active High.)

Bit 1 – Sync-on-Green Detect. It is set to Logic 1 if sync is present

on the Green video input; otherwise it is set to 0.

Bit 0 – Input Coast Polarity Detect. (Logic 0 = Active Low, Logic 1 =

Active High.)

15H

7:0

1111

****

Test Register

Bits [7:4] Reserved for future use.

****1***

Bit 3 – Must be set to 1 for proper operation.

*****1**

Bit 2 – Must be set to 1 for proper operation.

******1*

Bit 1 – 4:2:2 Output Formatting Mode (Logic 0 = 4:2:2 mode, Logic 1=

4:4:4 mode)

*******1

Bit 0 – Must be set to 0 for proper operation.

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