ADE3700SX datasheet(76/89 Pages) STMICROELECTRONICS

76 / 89 page

Output Multiplexer

ADE3700

76/89

eni = enab_in, hsi = hsync_in, vsi = vsync_in.

2.19.2 RSDS

In RSDS mode, clk and hsync outputs are the differential clock pair. All 48 data ports are combined

into neighboring pairs (e.g. orb0 and orb1 are differential pairs in RSDS mode). the lower index is

the positive sense differential output. TCON, data_enab and vsync outputs are unchanged.

data_enab and vsync can be used to output LVCMOS data inversion signals independent of RSDS

mode.

The following table indicates the pin, timing and data relationships in RSDS mode.

Table 29: Sync Mux Specification

enable data

OUT_MUX_CTRL0[0]

enable tcon

OUT_MUX_CTRL1[3]

ENAB_OUT

ENI

INV_A

HSYNC_OUT

HSI

TCI_GATED_CLK

VSYNC_OUT

VSI

INV_B

Table 30: TCON Mux Specification

enable tcon

OUT_MUX_CTRL1[3]

enable PWM

OUT_MUX_CTRL3[1]

PWM mux mode

OUT_MUX_CTRL3[2]

TCON_OUT7

TCI7

TCON_OUT6

TCI6

TCON_OUT5

TCI5

TCON_OUT4

TCI4

TCON_OUT3

TCI3

TCON_OUT2

TCI2

TCON_OUT1

TCI1

PWM_A

TCI1

TCON_OUT0

TCI0

PWM_B

TCI0

Table 31: RSDS Mode Specifications

RSDS Time

clk_o

hsync_o

o[r,g,b][a,b](2n)

o[r,g,b][a,b](2n+1)

bit from 2n

!bit from 2n

t+1

bit from 2n+1

!bit from 2n+1

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