ADE3700SX datasheet(12/89 Pages) STMICROELECTRONICS

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Global Control

ADE3700

12/89

MD = INT(fXCLK x (2

(6 + NDIV - SDIV)) / f

OUT)

PE = INT((2

15) x (MD + 1 - f

XCLK x (2

(6 + NDIV - SDIV)) / f

OUT))

where fXCLK is the external crystal frequency in MHz (typically 27). The maximum SCLK frequency

generated by this block is fXTAL x 2

(2+NDIV).

For the lowest power operation, all clock sources should be set to the “zero” setting and the analog

power disables should be set. In this condition, only the crystal clock domain (XCLK) is running and

blocks in INCLK or DOTCLK domains may not be accessible through the I²C interface.

The following modules can have their clocks disabled to reduce power consumption when the chip

is in steady-state mode: FLK, OSD, PGEN, DFT, and DMEAS. Also, the clock to the TCON can be

disabled for non-Smart Panel applications. Note that the OSD module has a special power bypass

bit that must be enabled when the OSD clock is disabled.

Also, the clock to all I²C registers associated with modules in the INCLK and DOTCLK domains can

be disabled after the chip is configured to reduce power in steady-state mode. Note that during chip

configuration, all I²C clocks must be enabled.

An asynchronous clock enable override signal must be disabled to allow control of individual

module clock signals.

fOUT < 2 x fXCLK AND fOUT ≥ fXCLK

fOUT < fXCLK AND fOUT ≥ fXCLK / 2

fOUT < fXCLK/2 AND fOUT ≥ fXCLK / 4

fOUT < fXCLK/4 AND fOUT ≥ fXCLK / 8

fOUT < fXCLK/8 AND fOUT ≥ fXCLK / 16

fOUT < fXCLK/16 AND fOUT ≥ fXCLK / 32

Table 3: SCLK Frequency Synthesizer Programmable Values (Sheet 2 of 2)

Frequency Range

SDIV

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