ADE3700SX datasheet(34/89 Pages) STMICROELECTRONICS

34 / 89 page

Sync Multiplexer (SMUX)

ADE3700

34/89

When hsync and/or vsync is generated (e.g. when enab is the only input), the relative position of the

generated pulse can be set either before or after the reference edge between -128 and +127 pixels

per line.

2.7.2

Example

ADC input using line lock clock:

omux_ctrl0 = 0x09

// select llk hsync and vsync

omux_ctrl1 = 0x0F

// choose incoming hsync and vsync as references, choose rising edges

omux_ctrl2 = 0x0C

// select the original hsyncs and vsyncs, along with the generated

// enab and valid signals

henab_set = hsync_width + hback_porch

henab_rst = hsync_width + hback_porch + in_hpixel

venab_set = vsync_width + vback_porch

venab_rst = vsync_width + vback_porch + in_vpixel

clamp_set = hsync_width + hback_porch + in_hpixel + 4 // clamp is turned on 4 after last pixel

clamp_rst = hsync_width + hback_porch -4 // clamp is turned off 4 pixels before the 1st pixel

Table 11: Sync Multiplexer Registers (Sheet 1 of 4)

Addr

Mode

Bits

Default

Description

SMUX_CTRL0

0x0200

[7:6]

0x0

Reserved

R/W

[5:3]

0x0

Vsync_internal select

0x0 = Reserved

0x1 = llk/VGA vsync

0x2 = Reserved

0x3 = composite sync decoder

0x4 = Reserved

R/W

[2:0]

0x0

Hsync_internal select

0x0 = Reserved

0x1 = llk synthesized hsync

0x2 = Reserved

0x3 = raw VGA hsync (jitter)

0x4 = Reserved

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