| 数据搜索系统,热门电子元器件搜索 |
|
ADE3700SX 数据表(PDF) 16 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
ADE3700SX 数据表(HTML) 16 Page - STMicroelectronics |
|
16 / 89 page ![]() FM Frequency Synthesizer ADE3700 16/89 2.2 FM Frequency Synthesizer The FM Frequency Synthesizer can create a clock up to eight times the crystal input clock using a digital frequency synthesizer. The modulation period and amplitude are directly controlled by I2C registers. The I2C interface runs in the LLK_CTRL clock domain, which must be active for access. The relationship of the output frequency (fOUT) to the 32-bit phase_rate value and the crystal frequency (fXCLK) is: fOUT = fXCLK * 2 27+NDIV / phase_rate where fOUT and fXCLK are in MHz. The maximum output frequency of the FM frequency synthesizer is fXTAL x 2 (2+NDIV). Note that native duty cycle of the FM frequency synthesizer is not 50/50, so it is recommended to either enable the divide-by-two in the fm synthesizer block for frequencies up to fXCLK x 2 (1+NDIV) (typically 108 MHz) or set the output mux to a double wide output mode for pixel clocks above fXCLK x2 (1+NDIV). This will ensure a 50% duty clock on the output. GLBL_INCLK_GATE_CTRL 0x0022 [7:3] 0x0 Reserved R/W [2] 0x1 Enable DFT clock R/W [1] 0x1 Enable DMEAS clock R/W [0] 0x1 Enable INCLK to I2C registers GLBL_DK_SRST 0x0040 [7] 0x0 Reserved R/W [6] 0x0 PGEN block reset synchronous to DOTCLK R/W [5] 0x0 OMUX block reset synchronous to DOTCLK R/W [4] 0x0 APC block reset synchronous to DOTCLK R/W [3] 0x0 OSD block reset synchronous to DOTCLK R/W [2] 0x0 GAMMA block reset synchronous to DOTCLK R/W [1] 0x0 OSQ block reset synchronous to DOTCLK R/W [0] 0x0 SCALE block reset synchronous to DOTCLK GLBL_OSD_POWER_CTRL 0x0041 [7:1] 0x0 Reserved R/W [0] 0x0 OSD bypass (when clock disabled) GLBL_DOTCLK_GATE_CTRL 0x0042 [7:5] 0x0 Reserved R/W [4] 0x1 Enable FLK clock R/W [3] 0x1 Enable TCON clock R/W [2] 0x1 Enable OSD clock R/W [1] 0x1 Enable PGEN clock R/W [0] 0x1 Enable DOTCLK to I2C registers Table 4: Global Registers (Sheet 4 of 4) Register Name Addr. mode Bits Default Description |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |