ADE3700SX datasheet(77/89 Pages) STMICROELECTRONICS

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ADE3700

Output Multiplexer

Note:

hsync_o is the positive clock signal according to the RSDS definition.

2.19.3 Per Pin Delay

Each of the 60 outputs has a per pin programmable delay. The delay is calibrated on the fly to the

XCLK period, which is assumed to be 37ns. Each pin can be delayed by up to 6ns in 0.4ns

increments. Code 0x0 is the least delay, code 0xF is the maximum delay. The setting is accurate to

±0.8ns across PVT. The calibration and resetting is done once per frame after the falling edge of

vertical enable to prevent glitches from delay mux changes in the active data period. The delays are

active in RSDS and normal output modes if enabled in the OUT_MUX_CTRL2 register.

t+2

bit from 2n

!bit from 2n

t+3

bit from 2n+1

!bit from 2n+1

Table 32: Output Mux Registers (Sheet 1 of 4)

Addr

Mode

Bits

Default

Description

OMUX_CTRL_0

0x0C30

R/W

[7]

0x0

in 2 ppc,

0: data invert for A+B comb.

1: data invert A/B separate

R/W

[6:4]

0x0

0x0 - 0x4: right shift per 8-bit R/G/B

0x5 - 0x7: Reserved

R/W

[3]

0x0

0: normal

1: flip msbs to lsbs

R/W

[2]

0x0

0: normal

1: swap R and B data

R/W

[1]

0x0

0: in 1 ppc, A channel active

0: in 2 ppc, Left on A, Right on B

1: in 1 ppc, B channel active

1: 2ppc, Left on B, Right on A

R/W

[0]

0x0

0: single wide, one pix/clk (ppc)

1: double wide, two pix/clk

OMUX_CTRL_1

0x0C31

R/W

[7]

0x0

Vsync Output Polarity

R/W

[6]

0x0

Hsync Output Polarity

R/W

[5]

0x0

Data Enable Output Polarity

R/W

[4]

0x0

Clock Output Invert

R/W

[3]

0x0

Data Invert Output Polarity

R/W

[2]

0x0

Data Invert Enable

R/W

[1]

0x0

0: TCON outputs set to zero

1: TCON outputs active

R/W

[0]

0x0

0: all data outputs set to zero

1: output enabled

Table 31: RSDS Mode Specifications (Continued)

RSDS Time

clk_o

hsync_o

o[r,g,b][a,b](2n)

o[r,g,b][a,b](2n+1)

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