25

AT86RF211

1942C–WIRE–06/02

Figure 33. Chronogram with Timing

Note:

For the timing specification, please refer to the timing table “Digital CMOS DC Characteristics” on page 42.

Registers

Note:

All the registers must be reprogrammed after the voltage supply has been removed, otherwise they will be in the default state

A[0]

A[1]

A[2]

A[3]

R/W

SCK

SDATA

SLE

D[9 ]

D[8]

D[7]

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

D[0]

INPUT

OUTPUT

INPUT

SDATA

direction

tdle

T

tw

thd

tsd

tpzon

tpd

tpzd

tdle

tw

Table 4. Registers Overview

Name

Address A[3:0]

Nbits

Read-Write

Comments

F0

(0000)

2

32

R-W

F0 Frequency Code

F1

32

R-W

F1 Frequency Code

F2

(0010)

2

32

R-W

F2 Frequency Code

F3

(0011)

2

32

R-W

F3 Frequency Code

CTRL1

32

R-W

Main Control Register

STAT

(0101)

2

31

R

Status Register

DTR

(0110)

2

6

R-W

Data Slicer Reference/Discriminator offset adjusting

WUC

32

R-W

Wake-up Control Register

WUR

(1000)

2

18

R-W

Wake-up Data Rate Register

WUA

(1001)

2

25

R-W

Wake-up Address Register

WUD

32

R

Wake-up Data Register

RESET

(1011)

2

1W

Reset

-

(1100)

2

Reserved

-

Reserved

-

(1110)

2

Reserved

CTRL2

(1111)

2

32

R-W

Control Register (Lock Detect - Clock Recovery)