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CS8413 数据表(PDF) 5 Page - List of Unclassifed Manufacturers |
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CS8413 数据表(HTML) 5 Page - List of Unclassifed Manufacturers |
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5 / 38 page ![]() CS8413 CS8414 DS240F1 5 SWITCHING CHARACTERISTICS - SERIAL PORTS (TA = 25 °C; VD+, VA+ = 5V ± 5%; Inputs: Logic 0 = DGND, Logic 1 = VD+; CL = 20 pF) Notes: 6. The output word rate, OWR, refers to the frequency at which an audio sample is output from the part. (A stereo pair is two audio samples.) Therefore, in Master mode, there are always 32 SCK periods in one audio sample. In Slave mode, exactly 32 SCK periods per audio sample must be provided in most serial port formats. Therefor, if SCK is 128 x Fs, then SCK must be gated to provide exactly 32 periods per audio sample. 7. In Master mode, SCK and FSYNC are outputs. In Slave mode, they are inputs. In the CS8413, control reg. 2 bit 1, MSTR, selects master. In the CS8414, formats 1, 3 and 9 are slaves. 8. The table above assumes data is output on the falling edge and latched on the rising edge. With the CS8413 the edge is selectable. The table is defined for the CS8413 with control reg. 2 bit 0, SCED, set to one, and for the CS8414 in formats 2, 3, 5, 6 and 7. For the other formats, the table and figure edges must be reversed (i.e. “rising” to “falling” and vice versa.) Parameters Symbol Min Typ Max Units SCK Frequency Master Mode (Notes 6 and 7) Slave Mode (Note 7) fsck - OWRx32 OWRx32 - - 128 x FS Hz Hz SCK falling to FSYNC delay Master Mode (Notes 7 and 8) tsfdm -20 - 20 ns SCK Pulse Width Low Slave Mode (Note 7) tsckl 40 - - ns SCK Pulse Width High Slave Mode (Note 7) tsckh 40 - - ns SCK rising to FSYNC edge delay Slave Mode (Notes 7 and 8) tsfds 20 - - ns FSYNC edge to SCK rising setup Slave Mode (Notes 7 and 8) tfss 20 - - ns SCK falling (rising) to SDATA valid (Note 8) tssv - - 20 ns C, U, CBL valid to FSYNC edge CS8414 (Note 8) tcuvf -1/fsck -s MCK to FSYNC edge delay FSYNC from RXN/RXP tmfd -15 - ns sfds t ssv t SDATA SCK FSYNC fss t MSB sckh t ssv t sckl t SDATA SCK FSYNC MSB (Mode 1) (Mode 3) sfdm t ssv t cuvf t SDATA SCK FSYNC C, U Serial Output Timing - Slave Mode Serial Output Timing - Master Mode & C, U Port FSYNC Generated From Received Data FSYNC mfd t MCK fss t sfds t sckh t sckl t SCK (Modes 2,3,5,6, 7,10,12, and 13) (Modes 0,1,4, 8,9, and 11) |
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