CS8413 datasheet(12/38 Pages) ETC

12 / 38 page

CS8413 CS8414

DS240F1

system-wide reset. After the user sets RST high, the

CS8413 comes fully out of reset when the block

boundary is found. The serial port, in master mode,

will begin to operate as soon as RST goes high. B0

and B1 select one of three buffer modes listed in

Table and illustrated in Figure 5. In all modes four

bytes of user data are stored. In mode 0, one entire

block of channel status is stored. In mode 1 eight

bytes of channel status and sixteen bytes of auxilia-

ry data are stored. In mode 2, eight bytes of channel

status from each sub-frame are stored. The buffer

modes are discussed in more detail in the Buffer

Memory section. The next bit, CS2/CS1, selects the

particular sub-frame of channel status to buffer in

modes 0 and 1, and has no effect in mode 2. When

CS2/CS1 is low, sub-frame 1 is buffered, and when

CS2/CS1 is high, sub-frame 2 is buffered. IER/SR

selects which set of registers, either IEnable or sta-

tus, occupy addresses 0 and 1. When IER/SR is

low, the status registers occupy the first two ad-

dresses, and when IER/SR is high, the IEnable reg-

isters occupy those addresses. FCEN enables the

internal frequency counter. A 6.144 MHz clock

must be connected to the FCK pin as a reference.

The value of the FREQ bits in SR2 are not valid un-

til two thirds of a block of data is received. Since

FCK and A4, the most significant address bit, oc-

cupy the same pin, A4 is internally set to zero when

FCEN is high. Since A4 is forced to zero, the upper

half of the buffer is not accessible while using the

frequency compare feature. FPLL determines how

FSYNC is derived. When FPLL is low, FSYNC is

derived from the incoming data, and when FPLL is

high, it is derived from the internal phase-locked

loop.

Control Register 2 configures the serial port which

consists of three pins: SCK, SDATA, and FSYNC.

SDATA is always an output, but SCK and FSYNC

can be configured as inputs or outputs. FSYNC and

SDATA can have a variety of relationships to each

other, and the polarity of SCK can be controlled.

The large variety of audio data formats provides an

easy interface to most DSPs and other audio pro-

cessors. SDATA is normally just audio data, but

special modes are provided that output received bi-

phase data, or received NRZ data with zeros substi-

tuted for preamble. Another special mode allows an

asynchronous SCK input to read audio data from

the serial port without slipping samples. In this

mode FSYNC and SDATA are outputs synchro-

nized to the SCK input. Since SCK is asynchronous

to the received clock, the number of SCK cycles

between FSYNC edges will vary.

ROER, when set, causes the last audio sample to be

reread if the error pin, ERF, is active. When out of

lock, the CS8413 will output zeros if ROER is set

Mode

Buffer Memory Contents

Channel Status

011

Auxiliary Data

Independent Channel Status

113

Reserved

Table 2. Buffer Memory Modes

CR1:

FPLL:

0 - FSYNC from RXP/RXN, 1 - FSYNC from PLL

FCEN:

enables freq. comparator (FCK must be 6.144 MHz).

IER/SR:

[X:00,01] 0 - status, 1 - interrupt enable registers.

CS2/CS1: ch. status to buffer; 0 - sub-frame 1, 1 - sub-frame 2.

B1:

with B0, selects the buffer memory mode.

B0:

with B1, selects the buffer memory mode.

RST:

Resets internal counters. Set to “1” for normal operation.

X:02

3210

CR1.

FPLL

FCEN

IER/SR

CS2/CS1

RST

Figure 8. Control Register 1

CR2:

ROER:

Repeat previous value on error (audio data)

SDF2:

with SDF0 & SDF1, select serial data format.

SDF1:

with SDF0 & SDF2, select serial data format.

SDF0:

with SDF1 & SDF2, select serial data format.

FSF1:

with FSF0, select FSYNC format.

FSF0:

with FSF1, select FSYNC format.

MSTR:

When set, SCK and FSYNC are output

SCED:

When set, falling edge of SCK outputs data.

When clear, rising edge of SCK outputs data.

X:03

76543210

CR2.

ROER

SDF2

SDF1

SDF0

FSF1

FSF0

MSTR

SCED

Figure 9. Control Register 2

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