P89LPC901FD datasheet(35/55 Pages) PHILIPS

35 / 55 page

Philips Semiconductors

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Product data

Rev. 04 — 21 November 2003

35 of 55

9397 750 12293

8.16.6

Timer overﬂow toggle output (P89LPC901)

Timers 0 and 1 can be conﬁgured to automatically toggle a port output whenever a

timer overﬂow occurs. The same device pins that are used for the T0 and T1 count

inputs are also used for the timer toggle outputs. The port outputs will be a logic 1

prior to the ﬁrst timer overﬂow when this mode is turned on.

8.17 Real-Time clock/system timer

The P89LPC901/902/903 has a simple Real-Time clock that allows a user to continue

running an accurate timer while the rest of the device is powered-down. The

Real-Time clock can be a wake-up or an interrupt source. The Real-Time clock is a

23-bit down counter comprised of a 7-bit prescaler and a 16-bit loadable down

counter. When it reaches all ‘0’s, the counter will be reloaded again and the RTCF

ﬂag will be set. The clock source for this counter can be either the CPU clock (CCLK)

or the XTAL oscillator, provided that the XTAL oscillator is not being used as the CPU

clock. If the XTAL oscillator is used as the CPU clock, then the RTC will use CCLK as

its clock source. Only power-on reset will reset the Real-Time clock and its

associated SFRs to the default state.

8.18 UART (P89LPC903)

The P89LPC903 has an enhanced UART that is compatible with the conventional

80C51 UART except that Timer 2 overﬂow cannot be used as a baud rate source.

The P89LPC903 does include an independent Baud Rate Generator. The baud rate

can be selected from the oscillator (divided by a constant), Timer 1 overﬂow, or the

independent Baud Rate Generator. In addition to the baud rate generation,

enhancements over the standard 80C51 UART include Framing Error detection,

automatic address recognition, selectable double buffering and several interrupt

options. The UART can be operated in 4 modes: shift register, 8-bit UART, 9-bit

UART, and CPU clock/32 or CPU clock/16.

8.18.1

Mode 0

Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are

transmitted or received, LSB ﬁrst. The baud rate is ﬁxed at 1

⁄

16 of the CPU clock

frequency.

8.18.2

Mode 1

10 bits are transmitted (through TxD) or received (through RxD): a start bit

(logical ‘0’), 8 data bits (LSB ﬁrst), and a stop bit (logical ‘1’). When data is received,

the stop bit is stored in RB8 in Special Function Register SCON. The baud rate is

variable and is determined by the Timer 1 overﬂow rate or the Baud Rate Generator

(described in Section 8.18.5 “Baud rate generator and selection”).

8.18.3

Mode 2

11 bits are transmitted (through TxD) or received (through RxD): start bit (logical ‘0’),

8 data bits (LSB ﬁrst), a programmable 9th data bit, and a stop bit (logical ‘1’). When

data is transmitted, the 9th data bit (TB8 in SCON) can be assigned the value of ‘0’ or

‘1’. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When

data is received, the 9th data bit goes into RB8 in Special Function Register SCON,

while the stop bit is not saved. The baud rate is programmable to either 1

⁄

16 or

⁄

32 of

the CPU clock frequency, as determined by the SMOD1 bit in PCON.

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