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CS8406-CS 数据表(PDF) 7 Page - Cirrus Logic

部件名 CS8406-CS
功能描述  192 KHZ DIGITAL AUDIO INTERFACE TRANSMITTER
PDF  43 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS8406-CS 数据表(HTML) 7 Page - Cirrus Logic

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CS8406
DS580F1
7
SWITCHING CHARACTERISTICS
(Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF)
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS
(Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF)
Notes: 5. The active edge of ISCLK is programmable in Software mode.
6. The polarity of ILRCK is programmable in Software mode.
7. Prevents the previous ISCLK edge from being interpreted as the first one after ILRCK has changed.
8. This setup time ensures that this ISCLK edge is interpreted as the first one after ILRCK has changed.
Parameter
Symbol
Min
Typ
Max
Units
RST pin Low Pulse Width
200
-
-
µs
OMCK Frequency for OMCK = 512*Fs
4.1
-
98.4
MHz
OMCK Low and High Width for OMCK = 512*Fs
4.1
-
-
ns
OMCK Frequency for OMCK = 384*Fs
3.1
-
73.8
MHz
OMCK Low and High Width for OMCK = 384*Fs
6.1
-
-
ns
OMCK Frequency for OMCK = 256*Fs
2.0
-
49.2
MHz
OMCK Low and High Width for OMCK = 256*Fs
8.1
-
-
ns
OMCK Frequency for OMCK = 128*Fs
1.0
-
24.6
MHz
OMCK Low and High Width for OMCK = 128*Fs
18.3
-
-
ns
Frame Rate
8
-
192
kHz
AES3 Transmitter Output Jitter
-
200
-
ps
Parameter
Symbol
Min
Typ
Max
Units
SDIN Setup Time Before ISCLK Active Edge
(Note 5)
tds
10
-
-
ns
SDIN Hold Time After ISCLK Active Edge
(Note 5)
tdh
8-
-
ns
Master Mode
OMCK to ISCLK active edge delay
(Note 5)
tsmd
0
-
17
ns
OMCK to ILRCK delay
(Note 6)
tlmd
0
-
16
ns
ISCLK and ILRCK Duty Cycle
-
50
-
%
Slave Mode
ISCLK Period
tsckw
36
-
-
ns
ISCLK Input Low Width
tsckl
14.4
-
-
ns
ISCLK Input High Width
tsckh
14.4
-
-
ns
ISCLK Active Edge to ILRCK Edge
(Note 7)
tlrckd
10
-
-
ns
ILRCK Edge Setup Before ISCLK Active Edge
(Note 8)
tlrcks
10
-
-
ns



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