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CS8406-CS 数据表(PDF) 29 Page - Cirrus Logic |
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CS8406-CS 数据表(HTML) 29 Page - Cirrus Logic |
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29 / 43 page ![]() CS8406 DS580F1 29 8.13 User Data Buffer Control (13h) UD - User bit data source specifier Default = ‘0’ 0 - U Pin is the source of transmitted U data 1 - U data buffer is the source of transmitted U data UBM1:0 - Sets the operating mode of the AES3 User bit manager Default = ‘00’ 00 - Transmit all zeros mode 01 - Block mode 10 - Reserved 11 - Reserved EFTUI - E to F U-data buffer transfer inhibit bit (valid in block mode only). Default = ‘0’ 0 - Allow U-data E to F buffer transfers 1 - Inhibit U-data E to F buffer transfers 8.14 Channel Status bit or User bit Data Buffer (20h - 37h) Either the channel status data buffer E or the separate user bit data buffer E (provided UBM bits are set to block mode) is accessible through these register addresses. 8.15 CS8406 I.D. and Version Register (7Fh) (Read Only) ID[3:0] - ID code for the CS8406. Permanently set to 1110 VER[3:0] = 0001 (revision A) VER[3:0] = 0010 (revision B) 7 6 5 43210 0 0 0 UD UBM1 UBM0 0 EFTUI 7 6 5 43210 ID3 ID2 ID1 ID0 VER3 VER2 VER1 VER0 |
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