CS8406

18

DS580F1

AES3 Transmitter in Stereo mode

U[0]

U[2]

Data [4]

Data [5]

Data [6]

Data [7]

Data [8]

Data [0]*

Data [2]*

Data [4]*

Z

Y

X

* Assume MMTLR = 0

Data [1]*

Data [3]*

Data [5]*

ZY

X

* Assume MMTLR = 1

•VLRCK is a virtual word clock, which may not exist, and is used to illustrate the CUV timing.

•VLRCK duty cycle is 50%.

•In stereo mode, VLRCK frequency = AES3 frame rate. In mono mode, VLRCK frequency = 2xAES3 frame rate.

•If the serial audio input port is on slave mode and TCBL is an output, then VLRCK = ILRCK if SILRPOL = 0

and VLRCK = ILRCK if SILRPOL =1.

•If the serial audio input port is in master mode and TCBL is an input, then VLRCK = ILRCK if SILRPOL = 0

and VLRCK = ILRCK if SILRPOL =1.

Tth

VCU[0]

VCU[1]

VCU[2]

VCU[3]

VCU[4]

VLRCK

V/C/U

(Input)

Data [4]

Data [5]

Data [6]

Data [7]

Data [8]

SDIN

(Input)

Data [0]

Data [1]

Data [2]

Data [3]

Data [4]

TXP(N)

(Output)

Z

Y

X

Y

X

Tsetup

Thold

Tth

Thold = 0

Tth > 3 OMCK clocks, if TCBL is Input

Tsetup

≥ 7.5% AES3 frame time

TCBL

(In/Output)

VLRCK

U

(Input)

SDIN

(Input)

TXP(N)

(Output)

TCBL

(In/Output)

TXP(N)

(Output)

AES3 Transmitter in Mono mode

Thold = 0

Tth > 3 OMCK clocks, if TCBL is Input

Tsetup

≥ 15% AES3 frame time

Figure 8. AES3 Transmitter Timing for C, U, and V Pin Input Data