CS8406-CS datasheet(36/43 Pages) CIRRUS

36 / 43 page

CS8406

DS580F1

12.APPLICATIONS

12.1 Reset, Power Down and Start-up

When RST is low, the CS8406 enters a low power mode and all internal states are reset, includ-

ing the control port and registers, and the outputs are disabled. In Software mode when RST is

high, the control port becomes operational and the desired settings should be loaded into the

control registers. Writing a 1 to the RUN bit will then cause the part to leave the low power state

and begin operation. In Hardware mode when RST is high, the part will automatically leave the

low power state and begin operation.

12.2 ID Code and Revision Code

The CS8406 has a register that contains a four-bit code to indicate that the addressed device is

a CS8406. This is useful when other CS84XX family members are resident in the same or similar

systems, allowing common software modules.

The CS8406 four-bit revision level code is also available. This allows the software driver for the

CS8406 to identify which revision of the device is in a particular system, and modify its behavior

accordingly. To allow for future revisions, it is strongly recommended that the revision code is

read into a variable area within the microcontroller, and used wherever appropriate as revision

details become known.

12.3 Power Supply, Grounding, and PCB layout

The CS8406 operates from a VD = +3.3 V or +5.0 V and VL = +3.3 V or +5.0 V supply. These

supplied may be set independently. Follow normal supply decoupling practices, see Figure 5 and

Figure 6. The VD and VL supplies should be decoupled with a 0.1

µF capacitor to GND to mini-

mize AES3 transmitter induced transients.

Extensive use of power and ground planes, ground plane fill in unused areas and surface mount

decoupling capacitors are recommended. Decoupling capacitors should be mounted on the

same side of the board as the CS8406 to minimize inductance effects, and all decoupling capac-

itors should be as close to the CS8406 as possible.

12.4 Synchronization of Multiple CS8406s

The AES3 transmitters of multiple CS8406s can be synchronized if all devices share the same

master clock, TCBL, and RST signals. The TCBL pin is used to synchronize multiple CS8406

AES3 transmitters at the channel status block boundaries. One CS8406 must have its TCBL set

to master; the others must be set to slave TCBL. Alternatively, TCBL can be derived from exter-

nal logic, whereby all CS8406 devices should be set to slave TCBL.

CS8406-CS 数据表(PDF) 36 Page - Cirrus Logic

CS8406-CS 数据表(HTML) 36 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

数据表下载