SLK2501

OC48/24/12/3 SONET/SDH MULTIRATE TRANSCEIVER

SLLS502A – OCTOBER 2001 – REVISED NOVEMBER 2001

4

POST OFFICE BOX 655303

Terminal Functions

clock pins

TERMINAL

TYPE

DESCRIPTION

NAME

NO.

TYPE

DESCRIPTION

REFCLKP,

REFCLKN

94

95

LVDS/PECL

compatible input

Differential reference input clock. There is an on-chip 100-

Ω termination resistor differentially

placed between REFCLKP and REFCLKN. The dc bias is also provided on-chip for ac-coupled

case.

TXCLKP,

TXCLKN

79

80

LVDS input

Transmit data clock. The data on TXDATA(0:3) is latched on the rising edge of TXCLKP.

TXCLKSRCP,

TXCLKSRCN

70

71

LVDS output

Transmit clock source. A clock source generated from the SLK2501 to the downstream device

(i.e., framer) that could be used by the downstream device to transmit data back to the SLK2501.

This clock is frequency-locked to the local reference clock.

RXCLKP,

RXCLKN

67

68

LVDS output

Receive data clock. The data on RXDATA(0:3) is on the falling edges of RXCLKP. The interface

of RXDATA(0:3) and RXCLKP is source synchronous (refer to Figure 7).

serial side data pins

TERMINAL

TYPE

DESCRIPTION

NAME

NO.

TYPE

DESCRIPTION

STXDOP,

STXDON

9

8

PECL compatible

output

Transmit differential pairs; high speed serial outputs.

SRXDIP,

SRXDIN

14

15

PECL compatible

input

Receive differential pairs; high speed serial inputs.

parallel side data pins

TERMINAL

TYPE

DESCRIPTION

NAME

NO.

TYPE

DESCRIPTION

TXDATA[0:3]

P/N

88–81

LVDS input

Transmit data pins. Parallel data on this bus is clocked on the rising edge of TXCLKP.

TXDATA0 is the first bit transmitted in time.

TXPARP,

TXPARN

99

98

LVDS input

Transmit data parity input

RXDATA[0:3]

P/N

66–63,

60–57

LVDS output

Receive data pins. Parallel data on this bus is valid on the falling edge of RXCLKP (refer to

Figure 7). RXDATA0 is the first bit received in time.

RXPARP,

RXPARN

56

55

LVDS output

Receive data parity output

FSYNCP,

FSYNCN

73

74

LVDS output

Frame sync pulse. This signal indicates the frame boundaries of the incoming data stream. If the

frame-detect circuit is enabled, FSYNC pulses for four RXCLKP and RXCLKN clock cycles,

when it detects the framing patterns.