SLK2501

OC48/24/12/3 SONET/SDH MULTIRATE TRANSCEIVER

SLLS502A – OCTOBER 2001 – REVISED NOVEMBER 2001

11

POST OFFICE BOX 655303

detailed description (continued)

signal detect

The SLK2501 has an input SIGDET pin to force the device into the loss of signal state. This pin is generally

connected to the signal detect output of the optical receiver. Depending on the optics manufacturer, this signal

can be either active high or active low. To accommodate the differences, a polarity select (PS) is used. For an

active low, SIGDET input sets the PS pin high. For an active high, SIGDET input sets the PS pin low. When the

PS signal pin and SIGDET are of opposite polarities, the loss of signal state is generated and the device

transmits all zeroes downstream.

multiplexer operation

The 4-bit parallel LVDS data is clocked into an input buffer by a clock derived from the synthesized clock. The

data is then clocked into a 4:1 multiplexer. The D0 bit is the most significant bit and is shifted out first in the serial

output stream.

demultiplexer operation

The serial 2.5 Gbps data is clocked into a 1:4 demultiplexer by the recovered clock. The D0 bit is the first bit

that is received in time from the input serial stream. The 4-bit parallel data is then sent to the LVDS driver along

with the divided down recovered clock.

frame synchronization

The SLK2501 has a SONET/SDH-compatible frame detection circuit that can be enabled or disabled by the

user. Frame detection is enabled when the FRAMEN pin is high. When enabled it detects the A1, A2 framing

pattern, which is used to locate and align the byte and frame boundaries of the incoming data stream. When

FRAMEN is low the frame detection circuitry is disabled and the byte boundary is frozen to the location found

when detection was previously enabled.

The frame detect circuit searches the incoming data for three consecutive A1 bytes followed immediately by

one A2 byte. The data alignment circuit then aligns the parallel output data to the byte and frame boundaries

of the incoming data stream. During the framing process the parallel data bus will not contain valid and aligned

data. Upon detecting the third A1, A2 framing patterns that are separated by 125

µs from each other, the FSYNC

signal goes high for four RXCLK cycles, indicating frame synchronization has been achieved.

The probability that random data in a SONET/SDH data stream will mimic the framing pattern in the data payload

is extremely low. However, there is a state machine built in to prevent false reframing if a framing pattern does

show up in the data payload.

testability

The SLK2501 has a comprehensive suite of built-in self-tests. The Loopback function provides for at-speed

testing of the transmit/receive portions of the circuitry. The enable pin allows for all circuitry to be disabled so

that an Iddq test can be performed. The PRBS function allows for a BIST (built-in self-test).

IDDQ function

When held low, the ENABLE pin disables all quiescent power in both the analog and digital circuitry. This allows

for Iddq testing on all power supplies and can also be used to conserve power when the link is inactive.

local loopback

The LLOOP signal pin controls the local loopback. When LLOOP is high, the loopback mode is activated and

the parallel transmit data is selected and presented on the parallel receive data output pins. The parallel transmit

data is also multiplexed and presented on the high-speed serial transmit pins. Local Loopback can only be

enabled when the device is under transceiver mode.