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SLK2501IPZP 数据表(PDF) 9 Page - Texas Instruments

部件名 SLK2501IPZP
功能描述  OC-48/24/12/3 SONET/SDH MULTIRATE TRANSCEIVER
PDF  20 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

SLK2501IPZP 数据表(HTML) 9 Page - Texas Instruments

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SLK2501
OC48/24/12/3 SONET/SDH MULTIRATE TRANSCEIVER
SLLS502A – OCTOBER 2001 – REVISED NOVEMBER 2001
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
detailed description (continued)
clock and data recovery
The CDR unit of SLK2501 recovers the clock and data from the incoming data streams.
In the event of receive data loss, the PLL automatically locks to the local REFCLK to maintain frequency stability.
If the frequency of the data differs by more that 100 ppm with respect to the REFCLK frequency, the LOL pin
is asserted as a warning. Actual loss of lock occurs if the data frequency differs by more than 170 ppm.
minimum transition density
The loop filter transfer function is optimized to enable the CDR to track ppm difference in the clocking and
tolerate the minimum transition density that can be received in a SONET data signal (
±20 ppm). The transfer
function yields a typical capture time of 3500 bit times for random incoming NRZ data after the device is powered
up and achieves frequency locking.
The device tolerates up to 72 consecutive digits (CID) without sustaining an error.
jitter transfer
The jitter transfer is less than the mask shown in Figure 2 (GR-253 Figure 5-27). Jitter transfer function is defined
as the ratio of jitter on the output signal to the jitter applied on the input signal versus frequency. The input
sinusoidal jitter amplitude is applied up to the mask level in the jitter tolerance requirement (see Figure 3).
OC-N/STS-N
LEVEL
fc
(kHz)
P
(dB)
3
12
24
48
130
500
2000
0.1
0.1
0.1
Not Specified
Slop = –20 dB / Decade
Frequency – kHz
fc
P
Figure 2. Jitter Transfer
jitter tolerance
Input jitter tolerance is defined as the peak to peak amplitude of sinusoidal jitter applied on the input signal that
causes the equivalent 1 dB optical/electrical power penalty. This refers to the ability of the device to withstand
input jitter without causing a recovered data error. The device has a jitter tolerance that exceeds the mask shown
in Figure 3 (GR-253 Figure 5-28). This jitter tolerance is specified using a pseudorandom data pattern of
231 –1.



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