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SLK2501IPZP 数据表(PDF) 6 Page - Texas Instruments |
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SLK2501IPZP 数据表(HTML) 6 Page - Texas Instruments |
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6 / 20 page ![]() SLK2501 OC48/24/12/3 SONET/SDH MULTIRATE TRANSCEIVER SLLS502A – OCTOBER 2001 – REVISED NOVEMBER 2001 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions(Continued) control/status pins (continued) TERMINAL TYPE DESCRIPTION NAME NO. TYPE DESCRIPTION PRBSPASS 42 TTL output PRBS test result. This pin reports the status of the PRBS test results (High = pass). When PRBSEN is disabled, the PRBSPASS pin is set low. When PRBSEN is enabled and a valid PRBS is received, then the PRBSPASS pin is set high. PAR_VALID 2 TTL output Parity checker output. The internal parity checker on the parallel side of the transmitter checks for even parity. If there is a parity error, the pin is pulsed low for two clock cycles. SPILL 49 TTL output TX FIFO collision output voltage supply and reserved pins TERMINAL TYPE DESCRIPTION NAME NO. TYPE DESCRIPTION VDDLVDS 62, 72, 75, 78, 90, 91, 92, 97 Supply LVDS supply voltage (2.5 V) GNDLVDS 61, 69, 76, 77, 89, 93, 96, 100 Ground LVDS ground VDD 3, 22, 25, 29, 32, 35, 50 Supply Digital logic supply voltage (2.5 V) GND 1, 6, 19, 23, 26, 28, 30, 31, 33, 40 Ground Digital logic ground VDDA 7, 16 Supply Analog voltage supply (2.5 V) GNDA 10, 13 Ground Analog ground VDDPLL 11 Supply PLL voltage supply (2.5 V) GNDPLL 12 Supply PLL ground RSVD 52 Reserved This pin needs to be tied to ground or left floating for normal operation. |
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