| 数据搜索系统,热门电子元器件搜索 |
|
SLK2501IPZP 数据表(PDF) 14 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
SLK2501IPZP 数据表(HTML) 14 Page - Texas Instruments |
|
14 / 20 page ![]() SLK2501 OC48/24/12/3 SONET/SDH MULTIRATE TRANSCEIVER SLLS502A – OCTOBER 2001 – REVISED NOVEMBER 2001 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating conditions (unless otherwise noted) TTL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIH High-level input voltage 2 3.6 V VIL Low-level input voltage 0.80 V IIH Input high current VDD = MAX, VIN = 2 V 40 µA IIL Input low current VDD = MAX, VIN = 4 V –40 µA VOH High-level output voltage IOH = –1 mA 2.10 2.3 V VOL Low-level output voltage IOH = 1 mA 0.25 0.5 V CI Input capacitance 4 pF LVDS input signals PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VI Input voltage 825 1575 mV VID(th) Input differential threshold voltage 100 mV CI Input capacitance 3 pF RI Input differential impedance On-chip termination 80 100 120 Ω tsu Input setup time requirement See Figure 8 300 ps th Input hold time requirement See Figure 8 300 ps T(duty) Input clock duty cycle 40% 60% LVDS output signals PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOD Output differential voltage 300 800 VOS Output common mode voltage R 100 ±1% 1070 1375 mV ∆VOD Change VOD between 1 and 0 RL = 100 ±1% 25 mV ∆VOS Change VOS between 1 and 0 25 I(SP), I(SN), I(SPN) Output short circuit current Outputs shorted to ground or shorted together 24 mA Ioff Power-off current VDD = 0 V 10 µA t(cq_min) Clock output time See Figure 7 100 ps t(cq_max) Clock-output time See Figure 7 100 ps tr/tf Output transition time 20%to80% 100 300 ps Output clock duty cycle 45% 55% Data output to FRAME_SYNC delay 4 7 Bit times timing requirements over recommended operating conditions (unless otherwise noted) reference clock (REFCLK) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Frequency tolerance† –20 20 ppm Duty cycle 40% 50% 60% Jitter 12 kHz to 20 MHz 3 ps rms Frequency range absolute value 622.08 MHz † The ±20 ppm tolerance is required to meet SONET/SDH requirements. For non-SONET/SDH compliant systems, looser tolerances may apply. |
|
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |