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ST72561 数据表(PDF) 63 Page - STMicroelectronics |
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ST72561 数据表(HTML) 63 Page - STMicroelectronics |
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63 / 262 page  ST72561 63/262 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d) Bit 0 = OIF Oscillator interrupt flag This bit is set by hardware and cleared by software reading the CSR register. It indicates when set that the main oscillator has reached the selected elapsed time (TB1:0). 0: Timeout not reached 1: Timeout reached CAUTION: The BRES and BSET instructions must not be used on the MCCSR register to avoid unintentionally clearing the OIF bit. Table 15. Main Clock Controller Register Map and Reset Values Address (Hex.) Register Label 76 54321 0 002Dh SICSR Reset Value 0 AVDIE AVDF LVDRF 0 00 WDGRF x 002Eh MCCSR Reset Value MCO 0 CP1 0 CP0 0 SMS 0 TB1 0 TB0 0 OIE 0 OIF 0 |
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