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ST72561 数据表(PDF) 13 Page - STMicroelectronics |
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ST72561 数据表(HTML) 13 Page - STMicroelectronics |
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13 / 262 page  ST72561 13/262 000Fh 0010h 0011h Port F PFDR PFDDR PFOR Port F Data Register Port F Data Direction Register Port F Option Register 00h1) 00h 00h R/W 2) R/W 2) R/W 2) 0012h to 0020h Reserved Area (15 Bytes) 0021h 0022h 0023h SPI SPIDR SPICR SPICSR SPI Data I/O Register SPI Control Register SPI Control/Status Register xxh 0xh 00h R/W R/W R/W 0024h FLASH FCSR Flash Control/Status Register 00h R/W 0025h 0026h 0027h 0028h 0029h 002Ah ITC ISPR0 ISPR1 ISPR2 ISPR3 EICR0 EICR1 Interrupt Software Priority Register 0 Interrupt Software Priority Register 1 Interrupt Software Priority Register 2 Interrupt Software Priority Register 3 External Interrupt Control Register 0 External Interrupt Control Register 1 FFh FFh FFh FFh 00h 00h R/W R/W R/W R/W R/W R/W 002Bh 002Ch AWU AWUCSR AWUPR Auto Wake up f. Halt Control/Status Register Auto Wake Up From Halt Prescaler 00h FFh R/W R/W 002Dh 002Eh CKCTRL SICSR MCCSR System Integrity Control / Status Register Main Clock Control / Status Register 0xh 00h R/W R/W 002Fh 0030h WWDG WDGCR WWDGR Watchdog Control Register Window Watchdog Register 7Fh 7Fh R/W R/W 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh PWM ART PWMDCR3 PWMDCR2 PWMDCR1 PWMDCR0 PWMCR ARTCSR ARTCAR ARTARR ARTICCSR ARTICR1 ARTICR2 Pulse Width Modulator Duty Cycle Register 3 PWM Duty Cycle Register 2 PWM Duty Cycle Register 1 PWM Duty Cycle Register 0 PWM Control register Auto-Reload Timer Control/Status Register Auto-Reload Timer Counter Access Register Auto-Reload Timer Auto-Reload Register ART Input Capture Control/Status Register ART Input Capture Register 1 ART Input Capture register 2 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h R/W R/W R/W R/W R/W R/W R/W R/W R/W Read Only Read Only 003Ch 003Dh 003Eh 003Fh 0040h 0041h 0042h 0043h 0044h 8-BIT TIMER T8CR2 T8CR1 T8CSR T8IC1R T8OC1R T8CTR T8ACTR T8IC2R T8OC2R Timer Control Register 2 Timer Control Register 1 Timer Control/Status Register Timer Input Capture 1 Register Timer Output Compare 1 Register Timer Counter Register Timer Alternate Counter Register Timer Input Capture 2 Register Timer Output Compare 2 Register 00h 00h 00h xxh 00h FCh FCh xxh 00h R/W R/W Read Only Read Only R/W Read Only Read Only Read Only R/W 0045h 0046h 0047h ADC ADCCSR ADCDRH ADCDRL Control/Status Register Data High Register Data Low Register 00h 00h 00h R/W Read Only Read Only Address Block Register Label Register Name Reset Status Remarks |
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