ST72561 datasheet(43/262 Pages) STMICROELECTRONICS

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ST72561

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POWER SAVING MODES (Cont’d)

Figure 27. ACTIVE-HALT Timing Overview

Figure 28. ACTIVE-HALT Mode Flow-chart

Notes:

1. This delay occurs only if the MCU exits

ACTIVE-HALT mode by means of a RESET.

2. Peripheral clocked with an external clock

source can still be active.

3. Only the RTC interrupt and some specific inter-

rupts can exit the MCU from ACTIVE-HALT

mode (such as external interrupt). Refer to

Table 8, “Interrupt Mapping,” on page 35 for

more details.

4. Before servicing an interrupt, the CC register is

pushed on the stack. The I[1:0] bits in the CC

level of the interrupt routine and restored when

the CC register is popped.

HALT

RUN

256 OR 4096 CYCLE

DELAY (AFTER RESET)

RESET

INTERRUPT

HALT

INSTRUCTION

FETCH

VECTOR

ACTIVE

(Active Halt enabled)

HALT INSTRUCTION

RESET

INTERRUPT 3)

CPU

OSCILLATOR

PERIPHERALS 2)

I[1:0] BITS

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

OSCILLATOR

PERIPHERALS

I[1:0] BITS

OFF

XX 4)

CPU

OSCILLATOR

PERIPHERALS

I[1:0] BITS

XX 4)

256 OR 4096 CPU CLOCK

CYCLE DELAY

(MCCSR.OIE=1)

(AWUCSR.AWUEN=0)

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