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ST72561 数据表(PDF) 51 Page - STMicroelectronics |
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ST72561 数据表(HTML) 51 Page - STMicroelectronics |
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51 / 262 page ![]() ST72561 51/262 I/O PORTS (Cont’d) 9.6 I/O Port Implementation The I/O port register configurations are summa- rised as following. 9.6.1 Standard Ports PB7:6, PC0, PC3, PC7:5, PD3:2, PD5, PE7:0, PF7:0 9.6.2 Interrupt Ports PA0,2,4,6; PB0,2,4; PC1; PD0,6 (with pull-up) PA1,3,5,7; PB1,3,5; PC2; PD1,4,7 (without pull-up) 9.6.3 Pull-up Input Port (CANTX requirement) PC4 The PC4 port cannot be controlled by DR/DDR/ OR in output. The CAN peripheral controls it di- rectly when enabled. Otherwise, it is pull-up input. However, it is still possible to read the port through DR register (providing DDR is set properly). MODE DDR OR floating input 0 0 pull-up input 0 1 open drain output 1 0 push-pull output 1 1 MODE DDR OR floating input 0 0 pull-up interrupt input 0 1 open drain output 1 0 push-pull output 1 1 MODE DDR OR floating input 0 0 floating interrupt input 0 1 open drain output 1 0 push-pull output 1 1 MODE pull-up input |
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