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ST72561 数据表(PDF) 29 Page - STMicroelectronics |
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ST72561 数据表(HTML) 29 Page - STMicroelectronics |
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29 / 262 page ![]() ST72561 29/262 SYSTEM INTEGRITY MANAGEMENT (Cont’d) 6.4.4 Register Description SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR) Read /Write Reset Value: 000x 000x (00h) Bit 7 = Reserved, must be kept cleared. Bit 6 = AVDIE Voltage Detector interrupt enable This bit is set and cleared by software. It enables an interrupt to be generated when the AVDF flag changes (toggles). The pending interrupt informa- tion is automatically cleared when software enters the AVD interrupt routine. 0: AVD interrupt disabled 1: AVD interrupt enabled Bit 5 = AVDF Voltage Detector flag This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an interrupt request is gen- erated when the AVDF bit changes value. Refer to Figure 16 and to Section 6.4.2.1 for additional de- tails. 0: VDD over VIT+(AVD) threshold 1: VDD under VIT-(AVD) threshold Bit 4 = LVDRF LVD reset flag This bit indicates that the last Reset was generat- ed by the LVD block. It is set by hardware (LVD re- set) and cleared by software (writing zero). See WDGRF flag description for more details. When the LVD is disabled by OPTION BYTE, the LVDRF bit value is undefined. Bits 3:1 = Reserved, must be kept cleared. Bit 0 = WDGRF Watchdog reset flag This bit indicates that the last Reset was generat- ed by the Watchdog peripheral. It is set by hard- ware (watchdog reset) and cleared by software (writing zero) or an LVD Reset (to ensure a stable cleared state of the WDGRF flag when CPU starts). Combined with the LVDRF flag information, the flag description is given by the following table. Application notes The LVDRF flag is not cleared when another RE- SET type occurs (external or watchdog), the LVDRF flag remains set to keep trace of the origi- nal failure. In this case, a watchdog reset can be detected by software while an external reset can not. CAUTION: When the LVD is not activated with the associated option byte, the WDGRF flag can not be used in the application. 70 0 AVD IE AVD F LVD RF 00 0 WDG RF RESET Sources LVDRF WDGRF External RESET pin 0 0 Watchdog 0 1 LVD 1 X |
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