STV6889 datasheet(27/56 Pages) STMICROELECTRONICS

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STV6889

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DESCRIPTION OF I²C-BUS SWITCHES AND FLAGS

Write-to bits

Sad00h/D7 - HDutySyncV

Synchronization of internal application of Hori-

zontal Duty cycle data, buffered in I²C-bus latch,

with internal discharge of Vertical oscillator.

0: Asynchronous mode, new data applied

with ACK bit of I²C-bus transfer on this sub

address

1: Synchronous mode

Sad02h/D7 - HMoiréMode

Horizontal Moiré characteristics.

0: Adapted to an architecture with EHT gener-

ated in deflection section

1: Adapted to an architecture with separated

deflection and EHT sections

Sad03h/D7 - B+SyncV

Same as HDutySyncV, applicable for B+ refer-

ence data

Sad06h/D7 - BOutPol

Polarity of B+ drive signal on BOut pin.

0: adapted to N type of power MOS - high

level to make it conductive

1: adapted to P type of power MOS - low level

to make it conductive

Sad07h/D7 - BOutPh

Phase of start of B+ drive signal on BOut pin

0: End of horizontal flyback or horizontal fre-

quency divided by 2, see BOHEdge bit.

1: With one of edges of line drive signal on

HOut

pin, selected by BOHEdge bit

Sad08h/D7 - EWTrHFr

Tracking of all corrections contained in wave-

form on pin EWOut with Horizontal Frequency

0: Not active

1: Active

Sad15h/D7 - VDyCorPol

Polarity of Vertical Dynamic Correction wave-

form (parabola)

0: Concave (minimum in the middle of the pa-

rabola)

1: Convex (maximum in the middle of the pa-

rabola)

Sad16h/D0 - HLockEn

Enable of output of Horizontal PLL1 Lock/unlock

status signal on pin HLckVBk

0: Disabled, vertical blanking only on the pin

HLckVBk

1: Enabled

Sad16h/D1 - PLL1InhEn

Enable of Inhibition of horizontal PLL1 during

extracted vertical synchronization pulse

0: Disabled, PLL1 is never inhibited

1: Enabled

Sad16h/D2 and D3- PLL1Pump

Horizontal PLL1 charge Pump current

Sad16h/D4 - SDetReset

Reset to 0 of Synchronization Detection flags

VDet, HVDet and VExtrDet of status register ef-

fected with ACK bit of I²C-bus data transfer into

description of the flags.

0: No effect

1: Reset with automatic return of the bit to 0

Sad16h/D5 - VSyncSel

Vertical Synchronization input Selection be-

tween the one extracted from composite HV sig-

nal on pin H/HVSyn and the one on pin VSyn. No

effect if VSyncAuto bit is at 1.

0: V. sync extracted from composite signal on

H/HVSyn

pin selected

1: V. sync applied on VSyn pin selected

Sad16h/D6 - VSyncAuto

Vertical Synchronization input selection Auto-

matic mode. If enabled, the device automatically

selects between the vertical sync extracted from

composite HV signal on pin H/HVSyn and the one

on pin VSyn, based on detection mechanism. If

both are present, the one coming first is kept.

0: Disabled, selection done according to bit

VSyncSel

1: Enabled, the bit VSyncSel has no effect

Time Constant

Slowest PLL1, lowest current

Moderate Slow PLL1, low current

Moderate Fast PLL1, high current

Fastest PLL1, highest current

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