STV6889 datasheet(30/56 Pages) STMICROELECTRONICS

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STV6889

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9 OPERATING DESCRIPTION

9.1 Supply and control

9.1.1

Power supply and voltage references

The device is designed for a typical value of power

supply voltage of 12 V.

In order to avoid erratic operation of the circuit at

power supply ramp-up or ramp-down, the value of

VCC is monitored. See Figure 1 and electrical spec-

ifications. At switch-on, the device enters a “nor-

mal operation” as the supply voltage exceeds VC-

CEn and stays there until it decreases bellow VC-

CDis. The two thresholds provide, by their differ-

ence, a hysteresis to bridge potential noise. Out-

side the “normal operation”, the signals on HOut,

BOut

and VOut outputs are inhibited and the I²C-

bus interface is inactive (high impedance on SDA,

SCL

pins, no ACK), all I²C-bus control registers be-

ing reset to their default values (see Chapter 8 -

page 25

). The stop of HOut and BOut drive signals

when the VCC falls from normal operation below

VCCDis is not instantaneous. It is only a trigger point

of Soft Stop mechanism (see Subsection 9.3.7- page

Figure 1. Supply voltage monitoring

Internal thresholds in all parts of the circuit are de-

rived from a common internal reference supply

VRefO that is lead out to RefOut pin for external filter-

ing against ground as well as for external use with

load currents limited to IRefO. The filtering is neces-

sary to minimize interference in output signals,

causing adverse effects like e.g. jitter.

9.1.2

I²C-bus control

The I²C-bus is a 2 line bidirectional serial commu-

nication bus introduced by Philips. For its general

description, refer to corresponding Philips I²C-bus

specification.

This device is an I²C-bus slave, compatible with

fast (400kHz) I²C-bus protocol, with write mode

slave address of 8Ch (read mode slave address

8Dh). Integrators are employed at the SCL (Serial

Clock) input and at the input buffer of the SDA (Se-

rial Data) input/output to filter off the spikes up to

50ns.

The device supports multiple data byte messages

(with automatic incrementing of the I²C-bus subad-

dress) as well as repeated Start Condition for I²C-

bus subaddress change inside the I²C-bus mes-

sages. All I²C-bus registers with specified I²C-bus

subaddress are of WRITE ONLY type, whereas

the status register providing a feedback informa-

tion to the master I²C-bus device has no attributed

I²C-bus subaddress and is of READ ONLY type.

The master I²C-bus device reads this register

sending directly, after the Start Condition, the

READ device I²C-bus slave address (8Dh) fol-

lowed by the register read-out, NAK (No Acknowl-

edge) signal and the Stop Condition.

For the I²C-bus control register map, refer to Chap-

ter 8 - page 25

9.2 Synchronization processor

9.2.1

Synchronization signals

The device has two inputs for TTL-level synchroni-

zation signals, both with hysteresis to avoid erratic

detection and with a pull-down resistor. On H/

HVSyn

input, pure horizontal or composite horizon-

tal/vertical signal is accepted. On VSyn input, only

pure vertical sync. signal is accepted. Both posi-

tive and negative polarities may be applied on ei-

ther input, see Figure 2. Polarity detector and pro-

grammable inverter are provided on each of the

two inputs. The signal applied on H/HVSyn pin, af-

ter polarity treatment, is directly lead to horizontal

part and to an extractor of vertical sync. pulses,

working on principle of integration, see Figure 3.

The vertical sync. signal applied to the vertical de-

flection processor is selected between the signal

extracted from the composite signal on H/HVSyn in-

put and the one applied on VSyn input. The selec-

tor is controlled by VSyncSel I²C-bus bit.

Besides polarity detection, the device is capable of

detecting presence of sync. signals on each of the

inputs and at the output of vertical sync. extractor.

The information from all detectors is provided in

the I²C-bus status register (5 flags: VDet, HVDet,

Normal operation

hysteresis

Disabled

V(Vcc)

VCC

VCCEn

VCCDis

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