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STV6889 数据表(PDF) 29 Page - STMicroelectronics

部件名 STV6889
功能描述  HIGH-END I²C CONTROLLED DEFLECTION PROCESSOR FOR MULTISYNC MONITOR
PDF  56 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STV6889 数据表(HTML) 29 Page - STMicroelectronics

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Read-out flags
SadXX/D0 - VDet(59)
Flag indicating Detection of V synchronization
pulses on VSyn pin.
0: Not detected
1: Detected
SadXX/D1 - HVDet (59)
Flag indicating Detection of H or HV synchroni-
zation pulses applied on H/HVSyn pin. Once the
sync pulses are detected, the flag is set and
latched. Disappearance of the sync signal will
not lead to reset of the flag.
0: Not detected
1: Detected.
SadXX/D2 - VExtrDet (59)
Flag indicating Detection of Extracted Vertical
synchronization signal from composite H+V sig-
nal applied on H/HVSyn pin.
0: Not detected
1: Detected
SadXX/D3 - VPol
Flag indicating Polarity of V synchronization
pulses applied on VSyn pin with respect to mean
level of the sync signal.
0: Positive
1: Negative
SadXX/D4 - HVPol
Flag indicating Polarity of H or HV synchroniza-
tion pulses applied on H/HVSyn pin with respect
to mean level of the sync signal.
0: Positive
1: Negative
SadXX/D5 - XRayAlarm
Alarm indicating that an event of excessive volt-
age has passed on XRay pin. Can only be reset
to 0 through I²C-bus bit XRayReset or by power-
on reset.
0: No excess since last reset of the bit
1: At least one event of excess appeared
since the last reset of the bit, HOut inhibited
SadXX/D6 - VLock
Status of “Locking” or stabilizing of Vertical oscil-
lator amplitude to an internal reference by AGC
regulation loop.
0: Locked (amplitude stabilized)
1: Not locked (amplitude non-stabilized)
SadXX/D7 - HLock
Lock status of Horizontal PLL1.
0: Locked
1: Not locked
See also bit Ident (Sad1Fh/D3)
Note 59: This flag, by its value of 1, indicates an event of detection of at least one synchronization pulse since its last
reset (by means of the SDetReset I²C-bus bit). This is to be taken into account by application S/W in a way that
enough time (at least the period between 2 synchronization pulses of analyzed signal) must be provided
between reset of the flag through SDetReset bit and validation of information provided in the flag after read-out
of status register.



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