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ADE3000SX 数据表(PDF) 76 Page - STMicroelectronics |
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ADE3000SX 数据表(HTML) 76 Page - STMicroelectronics |
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76 / 88 page  Output Mux Block ADE3XXX 76/88 OMUX_CTRL_2 0x0C32 R/W [7] 0x0 Seperate TCON Driven Invert Enable R/W [6] 0x0 TCON Driven Invert Pin Enable R/W [5] 0x0 RSDS enable R/W [4] 0x0 Per Pin Delay Enable R/W [3] 0x0 Resync on Vsync Falling Edge R/W [2] 0x0 Resync on Vsync Rising Edge R/W [1] 0x0 Resync on Hsync Falling Edge R/W [0] 0x0 Resync on Hsync Rising Edge OMUX_DLY_BA0 0x0C50 R/W [7:4] 0x0 Delay for OBA1 R/W [3:0] 0x0 Delay for OBA0 OMUX_ DLY_BA2 0x0C4F R/W [7:4] 0x0 Delay for OBA3 R/W [3:0] 0x0 Delay for OBA2 OMUX_ DLY_BA4 0x0C4E R/W [7:4] 0x0 Delay for OBA5 R/W [3:0] 0x0 Delay for OBA4 OMUX_ DLY_BA6 0x0C4D R/W [7:4] 0x0 Delay for OBA7 R/W [3:0] 0x0 Delay for OBA6 OMUX_ DLY_GA0 0x0C4C R/W [7:4] 0x0 Delay for OGA1 R/W [3:0] 0x0 Delay for OGA0 OMUX_ DLY_GA2 0x0C4B R/W [7:4] 0x0 Delay for OGA3 R/W [3:0] 0x0 Delay for OGA2 OMUX_ DLY_GA4 0x0C4A R/W [7:4] 0x0 Delay for OGA5 R/W [3:0] 0x0 Delay for OGA4 OMUX_ DLY_GA6 0x0C49 R/W [7:4] 0x0 Delay for OGA7 R/W [3:0] 0x0 Delay for OGA6 OMUX_ DLY_RA0 0x0C48 R/W [7:4] 0x0 Delay for ORA1 R/W [3:0] 0x0 Delay for ORA0 OMUX_ DLY_RA2 0x0C47 R/W [7:4] 0x0 Delay for ORA3 R/W [3:0] 0x0 Delay for ORA2 OMUX_ DLY_RA4 0x0C46 R/W [7:4] 0x0 Delay for ORA5 R/W [3:0] 0x0 Delay for ORA4 OMUX_ DLY_RA6 0x0C45 R/W [7:4] 0x0 Delay for ORA7 R/W [3:0] 0x0 Delay for ORA6 OMUX_ DLY_BB0 0x0C44 R/W [7:4] 0x0 Delay for OBB1 R/W [3:0] 0x0 Delay for OBB0 OMUX_ DLY_BB2 0x0C43 R/W [7:4] 0x0 Delay for OBB3 R/W [3:0] 0x0 Delay for OBB2 OMUX_ DLY_BB4 0x0C42 R/W [7:4] 0x0 Delay for OBB5 R/W [3:0] 0x0 Delay for OBB4 OMUX_ DLY_BB6 0x0C41 R/W [7:4] 0x0 Delay for OBB7 R/W [3:0] 0x0 Delay for OBB6 OMUX_ DLY_GB0 0x0C40 R/W [7:4] 0x0 Delay for OGB1 R/W [3:0] 0x0 Delay for OGB0 OMUX_ DLY_GB2 0x0C3F R/W [7:4] 0x0 Delay for OGB3 R/W [3:0] 0x0 Delay for OGB2 Table 29: Output Mux Registers (Sheet 2 of 3) Register Name Addr Mode Bits Default Description |
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