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ADE3000SX 数据表(PDF) 79 Page - STMicroelectronics |
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ADE3000SX 数据表(HTML) 79 Page - STMicroelectronics |
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79 / 88 page  79/88 ADE3XXX DFT Block 2.25 DFT Block Table 31: DFT Registers (Sheet 1 of 2) Register Name Addr Mode Bits Default Description DFT_TEST_MODE 0x0F00 [7:4] Reserved R/W [3] 0x0 trigger video bus MFSR R/W [2] 0x0 enable output pin MFSR R/W [1] 0x0 clear output pin MFSR R/W [0] 0x0 output pin test override DFT_MUX_OUT_MODE 0x0F01 [7:6] Reserved R/W [5:0] 0x0 mux selector for output porta/b and syncs DFT_FLOP_OUT_MODE 0x0F02 [7:6] Reserved R/W [5:0] 0x0 mux selector for synchronous digital debug bus DFT_CLK_0UT_MODE 0x0F03 R/W [7:6] 0x0 divide-by selector for clocks to OCLK pin fout = selected clock / (2 ^ value) R/W [5:0] 0x0 mux selector for clocks to OCLK pin DFT_CLK_1_MODE 0x0F04 R/W [7:6] 0x0 divide-by selector for clocks to CLKOUT pin fout = selected clock / (2 ^ value) DFT_CLK_2_MODE 0x0F05 R/W [5:0] 0x0 mux selector for clocks to CLKOUTpin DFT_OUT_DISAB_0 0x0F06 R/W [7:0] 0x0 disable porta red output in test mode DFT_OUT_DISAB_1 0x0F07 R/W [7:0] 0x0 disable porta green output in test mode DFT_OUT_DISAB_2 0x0F08 R/W [7:0] 0x0 disable porta blue output in test mode DFT_OUT_DISAB_3 0x0F09 R/W [7:0] 0x0 disable portb red output in test mode DFT_OUT_DISAB_4 0x0F0A R/W [7:0] 0x0 disable portb green output in test mode DFT_OUT_DISAB_5 0x0F0B R/W [7:0] 0x0 disable portb blue output in test mode DFT_OUT_DISAB_6 0x0F0C R/W [7:3] 0x0 disable tcon bits [4:0] in test mode R/W [2] 0x0 disable vert sync output in test mode R/W [1] 0x0 disable data enab output in test mode R/W [0] 0x0 disable horz sync output in test mode DFT_OUT_DISAB_7 0x0F0D [7:5] Reserved R/W [4] 0x0 disable CLKOUT output in test mode R/W [3] 0x0 disable OCLK output in test mode R/W [2:0] 0x0 disable tcon bits [7:5] in test mode DFT_STIM_CTRL 0x0F0E [7:6] Reserved R/W [0] 0x0 internal stimulus bus enable DFT_STIM_EN_0 0x0F0F R/W [7] 0x0 SCL test stimulus enable R/W [6] HDCP test stimulus enable R/W [5] DVI test mode enable R/W [4] DVI blue test stimulus enable R/W [3] DVI green test stimulus enable R/W [2] 0x0 DVI red test stimulus enable R/W [1] 0x0 ADC test stimulus enable R/W [0] 0x0 YUV test stimulus enable |
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