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ADE3000SX 数据表(PDF) 13 Page - STMicroelectronics

部件名 ADE3000SX
功能描述  LCD Display Engines with Integrated DVI, ADC and YUV Ports
PDF  88 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ADE3000SX 数据表(HTML) 13 Page - STMicroelectronics

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ADE3XXX
Global Control Block
2
ADE3XXX Functional Description
2.1
Global Control Block
The global control block is responsible for:
q
Selecting Clock Sources
q
Power Control
q
I²C Control
q
SCLK Frequency Synthesizer Control
q
Block-by-Block Synchronous Reset Generation
The global control block runs on the XCLK clock domain which is required to be active for
programming. The clock domains of all other blocks are set in the Global Control Block. For I²C
access, the requested block must be driven with a valid clock above 10 MHz. Clock domains are
shown in Figure 2.
To program the SCLK frequency synthesizer to a desired frequency (fout, in MHz), the following
equations apply:
Figure 2: Clock Domains
Table 3: SCLK Frequency Ranges
Frequency Range
SDIV
fOUT < 8 x fXCLK AND fOUT ≥ 4 x fXCLK
0
fOUT < 4 x fXCLK AND fOUT ≥ 2 x fXCLK
1
fOUT < 2 x fXCLK AND fOUT ≥ fXCLK
2
ADC (Analog)
DVI Rx (Analog)
YUV to RGB
SCLK
Freq.Synth.
Line Lock
PLL
Sync
Measure
I2C
Data
Measure
ADC Digital I/F
Scaler
Output
Sequencer
ADE3XXX
PC Analog
INR, G, B
V,H,CSYNC
DVI Link
RX0-2, RXC
FM Freq.
Synth.
Sync
Re-Time
TCON
Flicker
Detect
PWM
DVI Decoder
HDCP
YUV Video
YUV, YUVCLK
Global
Microcontroller
SCL, SDA
ORA, OGA, OBA
ORB, OGB, OBB
OCLK
ODE, OHS, OVS
TCON
DMUX
SMUX
data
data
data
INCLK
domain
SCLK
domain
DOTCLK
domain
XCLK
domain



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