ADE3000SX datasheet(78/88 Pages) STMICROELECTRONICS

78 / 88 page

Pulse Width Modulation (PWM) Block

ADE3XXX

78/88

Table 30: PWM Registers

Addr

Mode

Bits

Default

Description

PWM_CTRL0

0x01A0

[7]

0x0

PWM status

0: unlocked

1: locked

R/W

[6]

0x0

0: lock to CYCLES_PER_FRAME from the

free run state machine

1: lock to CYCLES_PER_FRAME register

setting

R/W

[5]

0x0

PWM_A polarity

0: active low

1: active high

R/W

[4]

0x0

PWM_B polarity

0: active low

1: active high

R/W

[3]

0x0

0: normal operation

1: force PWM outputs to polarity settings

R/W

[2]

0x0

0: change period or duty cycle at the end of

the current cycle

1: smooth change, period or duty cycle

increment/decrement every

PWM_STEP_DELAY cycle

R/W

[1]

0x0

0: free run

1: lock to out_vsync

R/W

[0]

0x0

0: disable PWM output

1: enable PWM output

PWM_CTRL1

0x01A1

R/W

[7:4]

0x0

Lock 2

nd order gain (power of 2)

0x0 = max

0x3 = typical

0xF = min

R/W

[3:0]

0x0

Lock gain (power of 2)

0x0 = max

0x6 = typical

0xF = min

PWM_PERIOD_L

0x01A2

R/W

[7:0]

0x0

Period-2 in Free-running mode, in XCLKs

PWM_PERIOD_H

0x01A3

R/W

[7:0]

PWM_DUTY_L

0x01A4

R/W

[7:0]

0x0

Duty cycle of PWM in XCLKs

PWM_DUTY_H

0x01A5

R/W

[7:0]

PWM_OVERLAP_L

0x01A6

R/W

[7:0]

0x0

Non-overlap of PWMs in XCLKs

PWM_OVERLAP_H

0x01A7

R/W

[7:0]

PWM_STEP_DELAY

0x01A8

R/W

[7:0]

0x0

In smooth change mode, the number of

cycles skipped before the period/duty

registers are incremented/decremented

PWM_CYCLES_PER_FRAME_L

0x01A9

R/W

[7:0]

0x0

The number of cycles per frame in frame

lock mode when not using the internally

generated cycles per frame from a previous

freerun mode

PWM_CYCLES_PER_FRAME_H

0x01AA

R/W

[7:0]

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