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PCK12429BD 数据表(PDF) 4 Page - NXP Semiconductors

部件名 PCK12429BD
功能描述  25-400 MHz differential PECL clock generator
PDF  14 Pages
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制造商  PHILIPS [NXP Semiconductors]
网页  http://www.nxp.com
标志 PHILIPS - NXP Semiconductors

PCK12429BD 数据表(HTML) 4 Page - NXP Semiconductors

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Philips Semiconductors
Product data
PCK12429
25–400 MHz differential PECL clock generator
2002 Jun 03
4
32-Pin LQFP
24
23
22
21
20
19
18
17
N/C
N[1]
N[0]
M[8]
M[7]
M[6]
M[5]
M[4]
1
2
3
4
5
6
7
8
32-LEAD LQFP
SW01012
S_CLOCK
S_DATA
S_LOAD
N/C
N/C
XTAL1
PLL-VCC
PLL-VCC
PIN DESCRIPTION
SYMBOL
FUNCTION
XTAL1, XTAL2
These pins form an oscillator when connected to an external series-resonant crystal.
S_LOAD (Int. pulldown)
This pin loads the configuration latches with the contents of the shift registers. The latches will be
transparent when this signal is HIGH, thus the data must be stable on the HIGH-to-LOW transition
of S_LOAD for proper operation.
S_DATA (Int. pulldown)
This pin acts as the data input to the serial configuration shift registers.
S_CLOCK (Int. pulldown)
This pin serves to clock the serial configuration shift registers. Data from S_DATA is sampled on the
rising edge.
P_LOAD (Int. pullup)
This pin loads the configuration latches with the contents of the parallel inputs. The latches will be
transparent when this signal is LOW, thus the parallel data must be stable on the LOW-to-HIGH
transition of P_LOAD for proper operation.
M[8:0] (Int. pullup)
These pins are used to configure the PLL loop divider. They are sampled on the LOW-to-HIGH
transition of P_LOAD, M[8] is the MSB, M[0] is the LSB.
N[1:0] (Int. pullup)
These pins are used to configure the output divider modulus. They are sampled on the
LOW-to-HIGH transition of P_LOAD.
OE (Int. pullup)
Active HIGH Output Enable. The Enable is synchronous to eliminate possibility of runt pulse
generation on the FOUT output.
FOUT, FOUT
These differential positive-referenced ECL signals (PECL) are the output of the synthesizer.
TEST
The function of this output is determined by the serial configuration bits T[2:0].
VCC1 and VCCO
This is the positive supply for the internal logic and the output buffer of the chip, and is connected to
+3.3 V (VCC = PLL_VCC).
PLL_VCC
This is the positive supply for the PLL, and should be as noise-free as possible for low-jitter
operation. This supply is connected to +3.3 V (VCC = PLL_VCC).
GND
These pins are the negative supply for the chip and are normally all connected to ground.



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