Philips Semiconductors

Product data

PCK12429

25–400 MHz differential PECL clock generator

2002 Jun 03

6

signal samples the information on the S_DATA line and loads it into

a 14-bit shift register. Note that the P_LOAD signal must be HIGH

for the serial load operation to function. The Test register is loaded

with the first three bits, the N register with the next two, and the M

register with the final eight bits of the data stream on the S_DATA

input. For each register the most significant bit is loaded first (T2,

N1, and M8). A pulse on the S_LOAD pin after the shift register is

fully loaded will transfer the divide values into the counters. The

HIGH_to_LOW transition on the S_LOAD input will latch the new

divide values into the counters. Figure 1 illustrates the timing

diagram for both a parallel and a serial load of the PCK12429

synthesizer.

M[8:0] and N[1:0] are normally specified once at power-up through

the parallel interface, and then possibly again through the serial

interface. This approach allows the application to come up at one

frequency and then change or fine-tune the clock as the ability to

control the serial interface becomes available. To minimize

transients in the frequency domain, the output should be varied in

the smallest step size possible. The bandwidth of the PLL is such

that frequency stepping in 1 MHz steps at the maximum S_CLOCK

frequency or less will cause smooth, controlled slewing of the output

frequency.

The TEST output provides visibility for one of the several internal

nodes as determined by the T[2:0] bits in the serial configuration

stream. It is not configurable through the parallel interface. Although

output may may not be able to toggle fast enough for some of the

higher output frequencies. The T2, T1, and T0 control bits are preset

as jitter-free as possible. Any active signal on the TEST output pin

will have detrimental affects on the jitter of the PECL output pair. In

normal operations, jitter specifications are only guaranteed if the

TEST output is static. The serial configuration port can be used to

select one of the alternate functions for this pin.

Most of the signals available on the TEST output pin are useful only

for performance verification of the PCK12429 itself. However, the

PLL bypass mode may be of interest at the board level for functional

debug. When T[2:0] is set to 110 the PCK12429 is placed in PLL

bypass mode. In this mode the S_CLOCK input is fed directly into

and the M counter drives the TEST output pin. In this mode the

S_CLOCK input could be used for low speed broad level functional

the user more control on the test clocks sent through the clock tree.

Figure 2 shows the functional setup of the PLL bypass mode.

Because the S_CLOCK is a CMOS level the input frequency is

be toggled via the S_CLOCK is 125 MHz, as the minimum divide

ratio of the N counter is 2. Note that the M counter output on the

TEST output will not be a 50% duty cycle due to the way the divider

is implemented.

Table 1. Test modes

T2

T1

T0

TEST (Pin 20)

0

0

0

SHIFT REGISTER OUT

0

0

1

HIGH

0

1

0

0

1

1

M COUNTER OUT

1

0

0

1

0

1

LOW

1

1

0

PLL BYPASS

1

1

1

S_CLOCK

SW00729

T2

S_DATA

T1 T0 N1 N0 M8 M7 M6 M5 M4 M3 M2 M1

M0

S_LOAD

First

Bit

Last

Bit

M, N

M[8:0]

N[1:0]

P_LOAD

Figure 1. Timing Diagram