Philips Semiconductors

Product data

PCK12429

25–400 MHz differential PECL clock generator

2002 Jun 03

7

SW00730

N DIVIDE

(2, 4, 8, 16)

PLL 12429

SHIFT

REG

14-BIT

VCO_CLK

MCNT

0

1

(VIA ENABLE GATE)

SEL_CLK

SCLOCK

SDATA

T0

T1

T2

DECODE

LATCH

Reset

M COUNTER

SLOAD

PLOADB

FDIV4

MCNT

LOW

MCNT

HIGH

TEST

MUX

0

7

TEST

• T2 = T1 = 1. T0 = 0: Test Mode

PLOADB acts as reset for test pin latch. When latch reset T2 data is shifted out TEST pin.

Figure 2. Serial Test Clock Block Diagram

SYMBOL

PARAMETER

CONDITION

LIMITS

UNIT

SYMBOL

PARAMETER

CONDITION

MIN

TYP

MAX

UNIT

Input HIGH Voltage

2.0

—

—

V

Input LOW Voltage

—

—

0.8

V

Input Current

—

—

1.0

mA

Output HIGH Voltage

TEST

2.5

—

V

Output LOW Voltage

TEST

—

—

0.4

V

Output HIGH Voltage

217

250

V

Output HIGH Voltage

CC0

(Notes 1 and 2)

2.17

—

2.50

V

Output LOW Voltage

141

176

V

Output LOW Voltage

CC0

(Notes 1 and 2)

1.41

—

1.76

V

Power Supply Current

85

100

mA

Power Supply Current

—

15

20

mA

NOTES:

2. 50