Philips Semiconductors

Product data

PCK12429

25–400 MHz differential PECL clock generator

2002 Jun 03

9

Power supply filtering

The PCK12429 is a mixed analog/digital product and as such it

exhibits some sensitivities that would not necessarily be seen on a

fully digital product. Analog circuitry is naturally susceptible to

random noise, especially if this noise is seen on the power supply

pins. The PCK12429 provides separate power supplies for the

The purpose of this design technique is to try and isolate the high

switching noise digital outputs from the relatively sensitive internal

analog phase-locked loop. In a controlled environment such as an

evaluation board, this level of isolation is sufficient. However, in a

digital system environment where it is more difficult to minimize

noise on the power supplies, a second level of isolation may be

required. The simplest form of isolation is a power supply filter on

Figure 3 illustrates a typical power supply filter scheme. The

PCK12429 is most susceptible to noise with spectral content in the

1 kHz to 2 MHz range. A good choice of pole placement should be

close to 32 kHz. Therefore the filter should be designed to target this

range. The key parameter that needs to be met in the final filter

is typically 15 mA (20 mA maximum), assuming that a minimum of

shown in Figure 3 must have a resistance of 10–15

Ω to meet the

voltage drop criteria. The RC filter pictured will provide a broadband

filter with approximately 100:1 attenuation for noise whose spectral

content is above 20 kHz. As the noise frequency crosses the series

resonant point of an individual capacitor, its overall impedance

begins to look inductive and thus increases with increasing

frequency. The parallel capacitor combination shown ensures that a

low impedance path to ground exists for frequencies well above the

bandwidth of the PLL.

SW00745

PCK12429

0.01

µF

22

µF

L = 1000

µH

R = 15

Ω

3.3 V

3.3 V

Figure 3. Power supply filter

A higher level of attenuation can be achieved by replacing the

resistor with an appropriate valued inductor. Figure 3 shows a

1000

µH choke, this value choke will show a significant impedance

at 10 KHz frequencies and above. Because of the current draw and

resistance inductor is required (less than 15

Ω). Generally the

resistor/capacitor filter will be cheaper, easier to implement, and

provide an adequate level of supply filtering.

The PCK12429 provides sub-nanosecond output edge rates, and

thus a good power supply bypassing scheme is a must. Figure 4

shows a representative board layout for the PCK12429. There exists

many different potential board layouts and the one pictured is but

one. The important aspect of the layout in Figure 4 is the low

capacitors. Combining good quality general purpose chip capacitors

with good PCB layout techniques will produce effective capacitor

resonances at frequencies adequate to supply the instantaneous

switching current for the PCK12429 outputs. It is imperative that low

inductance chip capacitors are used; it is equally important that the

board layout does not introduce back all of the inductance saved by

using the leadless capacitors. Thin interconnect traces between the

capacitor and the power plane should be avoided and multiple large

vias should be used to tie the capacitors to the buried power planes.

Fat interconnect and large vias will help to minimize layout induced

inductance and thus maximize the series resonant point of the

bypass capacitors.

SW00746

Xtal

1

C3

C2

= VCC

= GND

= Via

C1

C1

R1 = 10–15

Ω

C1 = 0.01

µF

C2 = 22

µF

C3 = 0.1

µF

R1

Figure 4. PCB board layout for PCK12429

Note the dotted lines circling the crystal oscillator connection to the

device. The oscillator is a series resonant circuit and the voltage

amplitude across the crystal is relatively small. It is imperative that

no actively switching signals cross under the crystal, as crosstalk

energy coupled to these lines could significantly impact the jitter of

the device. Special attention should be paid to the layout of the

crystal to ensure a stable, jitter free interface between the crystal

and the on-board oscillator.

Although the PCK12429 has several design features to minimize the

susceptibility to power supply noise (isolated power and grounds

and fully differential PLL) there still may be applications in which

overall performance is being degraded due to system power supply

noise. The power supply filter and bypass schemes discussed in this

section should be adequate to eliminate power supply noise related

problems in most designs.