Philips Semiconductors

Product data

PCK12429

25–400 MHz differential PECL clock generator

2002 Jun 03

5

BLOCK DIAGRAM

XTAL1

SW00728

OSC

XTAL2

DIV 16

1 MHz

PHASE

DETECTOR

VCO

9-BIT DIV M

COUNTER

LATCH

200–400

MHz

DIV N

(1, 2, 4, 8)

+3.3 V

LATCH

16 MHz

OE

01

01

LATCH

TEST

S_LOAD

P_LOAD

9-BIT

SR

2-BIT

SR

3-BIT

SR

S_DATA

S_CLOCK

+3.3 V

9

M[8:0]

2

N[1:0]

+3.3 V

N[1:0]

Output Division

0 0

0 1

1 0

1 1

1

2

4

8

PROGRAMMING INTERFACE

Programming the device amounts to properly configuring the internal

dividers to produce the desired frequency at the outputs. The output

frequency can be represented by this formula:

(1)

and N is the output divider modulus. Note that it is possible to select

values of M such that the PLL is unable to achieve loop lock. To

avoid this, always make sure that M is selected to be 200

≤ M ≤ 400

for a 16 MHz input reference.

Assuming that a 16 MHz reference frequency is used, the above

equation reduces to:

Substituting the four values for N (1, 2, 4, or 8) yields:

for 200

≤ M ≤ 400

The user can identify the proper M and N values for the desired

frequency from the above equations. The four output frequency

ranges established by N are 200–400 MHz, 100–200 MHz,

50–100 MHz, and 25–50 MHz respectively. From these ranges the

user will establish the value of N required, then the value of M can

be calculated based on the appropriate equation above. For

example, if an output frequency of 131 MHz was desired, the

following steps would be taken to identify the appropriate M and N

values. 131 MHz falls within the frequency range set by an N value

Therefore, M = 131

× 2 = 262, so M[8:0] = 100000110. Following this

same procedure a user can generate any whole frequency desired

between 25 and 400 MHz. Note that for N

≥ 2 fractional values of

steps (and thus the indicator of the fractional output frequencies

For input reference frequencies other than 16 MHz, the set of

appropriate equations can be deduced from equation 1. For

computer applications another useful frequency base would be

16.666 MHz. From this reference, one can generate a family of

output frequencies at multiples of the 33.333 MHz PCI clock. As an

example, to generate a 133.333 MHz clock from a 16.666 MHz

reference, the following M and N values would be used:

Let N = 2, M = 256,

The value for M falls within the constraints set for PLL stability,

therefore N[1:0] = 01 and M[8:0] = 100000000. If the value for M fell

outside of the valid range a different N value would be selected to try

to move M in the appropriate direction.

The M and N counters can be loaded either through a parallel or

serial interface. The parallel interface is controlled via the P_LOAD

signal such that a LOW to HIGH transition will latch the information

present on the M[8:0] and N[1:0] inputs into the M and N counters.

When the P_LOAD signal is LOW the input latches will be

transparent and any changes on the M[8:0] and N[1:0] inputs will