MCP3913 datasheet(21/82 Pages) MICROCHIP

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DS20005227A-page 21

MCP3913

4.0

TERMINOLOGY AND

FORMULAS

This section defines the terms and formulas used

throughout this data sheet. The following terms are

defined:

• MCLK – Master Clock

• AMCLK – Analog Master Clock

• DMCLK – Digital Master Clock

• DRCLK – Data Rate Clock

• OSR – Oversampling Ratio

• Offset Error

• Gain Error

• Integral Non-Linearity Error

• Signal-to-Noise Ratio (SNR)

• Signal-To-Noise Ratio And Distortion (SINAD)

• Total Harmonic Distortion (THD)

• Spurious-Free Dynamic Range (SFDR)

• MCP3913 Delta-Sigma Architecture

• Idle Tones

• Dithering

• Crosstalk

• PSRR

• CMRR

• ADC Reset Mode

• Hard Reset Mode (RESET = 0)

• ADC Shutdown Mode

• Full Shutdown Mode

• Measurement Error

4.1

MCLK – Master Clock

This is the fastest clock present on the device. This is

the frequency of the crystal placed at the OSC1/OSC2

inputs when CLKEXT = 0, or the frequency of the

clock input at the OSC1/CLKI when CLKEXT = 1. See

Figure 4-1.

4.2

AMCLK – Analog Master Clock

AMCLK is the clock frequency that is present on the

analog portion of the device, after prescaling has

occurred via the CONFIG0 PRE<1:0> register bits (see

Equation 4-1). The analog portion includes the PGAs

and the delta-sigma modulators.

EQUATION 4-1:

FIGURE 4-1:

Clock Sub-Circuitry.

4.3

DMCLK – Digital Master Clock

This is the clock frequency that is present on the digital

portion of the device, after prescaling and division by

four (Equation 4-2). This is also the sampling

frequency, which is the rate at which the modulator

outputs are refreshed. Each period of this clock

corresponds to one sample and one modulator output.

See Figure 4-1.

EQUATION 4-2:

4.4

DRCLK – Data Rate Clock

This is the output data rate, i.e., the rate at which the

ADCs output new data. Each new data is signaled by a

data ready pulse on the DR pin.

This data rate is depending on the OSR and the

prescaler with the formula in Equation 4-3.

EQUATION 4-3:

TABLE 4-1:

MCP3913 OVERSAMPLING

RATIO SETTINGS

Config.

Analog Master Clock

Prescale

PRE<1:0>

AMCLK = MCLK/1 (default)

AMCLK = MCLK/2

AMCLK = MCLK/4

AMCLK = MCLK/8

AMCLK

MCLK

PRESCALE

-------------------------------

Xtal Oscillator

MCLK

OSC1

OSC2

Multiplexer

OUT

1/PRESCALE

1/4

1/OSR

AMCLK

DMCLK

DRCLK

Clock Divider

OSR<2:0>

PRE<1:0>

CLKEXT

Multiplexer

OUT

MODE

SCK

DMCLK

AMCLK

---------------------

MCLK

PRESCALE



----------------------------------------

DRC LK

DMC LK

OSR

----------------------

AMCLK

4OSR



---------------------

MCLK

OSR

PRESCALE



-----------------------------------------------------------

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