MCP3913 datasheet(41/82 Pages) MICROCHIP

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DS20005227A-page 41

MCP3913

6.0

SPI SERIAL INTERFACE

DESCRIPTION

6.1

Overview

The MCP3913 device includes a four-wire (CS, SCK,

SDI, SDO) digital serial interface that is compatible with

SPI Modes 0,0 and 1,1. Data is clocked out of the

MCP3913 on the falling edge of SCK, and data is

clocked into the MCP3913 on the rising edge of SCK.

In these modes, the SCK clock can idle either high (1,1)

or low (0,0). The digital interface is asynchronous with

the MCLK clock that controls the ADC sampling and

digital filtering. All the digital input pins are Schmitt-

triggered to avoid system noise perturbations on the

communications.

Each SPI communication starts with a CS falling edge

and stops with the CS rising edge. Each SPI communi-

cation is independent. When CS is logic high, SDO is

in high-impedance, transitions on SCK, and SDI have

no effect. Changing from an SPI Mode 1,1 to an SPI

Mode 0,0 and vice versa is possible and can be done

while the CS pin is logic high. Any CS rising edge clears

the communication and resets the SPI digital interface.

Additional control pins (RESET, DR) are also provided

on separate pins for advanced communication

features. The Data Ready pin (DR) outputs pulses

when a new ADC channel data is available for reading,

which can be used as an interrupt for an MCU. The

master reset pin (RESET) acts like a hard reset and

can reset the part to its default power-up configuration

(equivalent to a POR state).

The MCP3913 interface has a simple command

structure. Every command is either a READ command

from a register, or a WRITE command to a register. The

MCP3913 device includes 32 registers defined in the

Table 8-1 register map. The first byte (8-bit wide)

transmitted is always the CONTROL byte that defines

the address of the register and the type of command

(Read or Write). It is followed by the register itself,

which can be in a 16-, 24- or 32-bit format, depending

on the multiple format settings defined in the

STATUSCOM register. The MCP3913 is compatible

with multiple formats that help reduce overhead in the

data handling for most MCUs and processors available

on the market (8-/16- or 32-bit MCUs) and improve

MCU-code compaction and efficiency.

The MCP3913 digital interface is capable of handling

various continuous read and write modes, which allow

it to perform ADC data streaming or full register map

writing within only one communication (and therefore

with only one unique control byte). The internal

registers can be grouped together with various

configurations through the READ<1:0> and WRITE

bits. The internal address counter of the serial interface

can be automatically incremented with no additional

control byte needed, in order to loop through the

various groups of registers within the register map. The

groups are defined in Table 8-2.

The MCP3913 device also includes advanced security

features to secure each communication, to avoid

unwanted write commands being processed to change

the desired configuration, and to alert the user in case

of a change in the desired configuration.

Each SPI read communication can be secured through

a selectable CRC-16 checksum provided on the SDO

pin at the end of every communication sequence. This

CRC-16 computation is compatible with the DMA CRC

hardware of the PIC24 and PIC32 MCUs, resulting in

no additional overhead for the added security.

For securing the entire configuration of the device, the

MCP3913 includes an 8-bit lock code (LOCK<7:0>),

which blocks all write commands to the full register

map if the value of the LOCK<7:0> is not equal to a

defined password (0xA5). The user can protect its

configuration by changing the LOCK<7:0> value to

0x00 after the full programming, so that any unwanted

write command will not result in a change to the

configuration (because LOCK<7:0> is different than the

password 0xA5).

An additional CRC-16 calculation is also running con-

tinuously in the background to ensure the integrity of

the full register map. All writable registers of the regis-

ter map (except the MOD register) are processed

through a CRC-16 calculation engine and give a CRC-

16 checksum that depends on the configuration. This

checksum is readable on the LOCK/CRC register and

updated at all times. If a change in this checksum hap-

pens, a selectable interrupt can give a flag on the DR

pin (DR pin becomes logic low) to warn the user that

the configuration is corrupted.

6.2

Control Byte

The control byte of the MCP3913 contains two device

Address bits (A<6:5>), five register Address bits

(A<4:0>) and a Read/Write bit (R/W). The first byte

transmitted to the MCP3913 in any communication is

always the control byte. During the control byte trans-

fer, the SDO pin is always in a high-impedance state.

The MCP3913 interface is device addressable

(through A<6:5>), so that multiple chips can be present

on the same SPI bus with no data bus contention, even

if they use the same CS pin, they use a provided half-

duplex SPI interface, with a different address identifier.

This functionality enables, for example, a Serial

EEPROM like 24AAXXX/24LCXXX or 24FCXXX and

the MCP3913 to share all the SPI pins and consume

less I/O pins in the application processor, since all

these Serial EEPROM circuits use A<6:5> = 00.

FIGURE 6-1:

Control Byte.

A<6> A<5> A<4> A<3> A<2> A<1> A<0> R/W

Device

Address

Read/

Write

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