MCP3913 datasheet(39/82 Pages) MICROCHIP

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 2013 Microchip Technology Inc.

DS20005227A-page 39

MCP3913

FIGURE 5-8:

DR_LINK Configurations.

The external clock should not be higher than 20 MHz

before

prescaling

(MCLK < 20 MHz)

for

proper

operation.

5.13

Digital System Offset and Gain

Calibration Registers

The MCP3913 incorporates two sets of additional

registers per channel to perform system digital offset

and gain error calibration. Each channel has its own set

of associated registers that will modify the output result

of the channel, if calibration is enabled. The gain and

offset calibrations can be enabled or disabled through

two CONFIG0 bits (EN_OFFCAL and EN_GAINCAL).

These two bits enable or disable system calibration on

all channels at the same time. When both calibrations

are enabled, the output of the ADC is modified per

Equation 5.13.1.

5.13.1

DIGITAL OFFSET ERROR

CALIBRATION

The OFFCAL_CHn registers are 23-bit plus two’s

complement registers, and whose LSB value is the

same as the Channel ADC Data. These registers are

added bit by bit to the ADC output codes, if the

EN_OFFCAL bit is enabled. Enabling the EN_OFFCAL

bit does not create a pipeline delay; the offset addition

is instantaneous. For low OSR values, only the

significant digits are added to the output (up to the

resolution of the ADC; for example, at OSR = 32, only

the 17 first bits are added).

The offset is not added when the corresponding

channel is in Reset or Shutdown mode. The

corresponding input voltage offset value added by each

LSB in these 24-bit registers is:

This registers are a “Don't Care” if EN_OFFCAL = 0

(offset calibration disabled), but their value is not

cleared by the EN_OFFCAL bit.

One DRCLK period (OSR times DMCLK periods)

DR_LINK=1

Only the most lagging data ready is present

All channels are latched together at DR

falling edge

DR_LINK=0

All channels data

ready are present

Data ready pulse from odd

channels (reference)

PHASE=0

Data ready pulse from odd

channels (reference)

PHASE=0

PHASE<0

PHASE>0

Data ready pulse from

most lagging ADC channel

Data ready pulse from

most lagging ADC channel

Note:

In addition to the conditions defining the

maximum MCLK input frequency range,

the

AMCLK

frequency

should

maintained inferior to the maximum limits

defined in Table 5-2, to ensure the

accuracy of the ADCs. If these limits are

exceeded, it is recommended to choose

either a larger OSR, or a larger prescaler

value so that AMCLK can respect these

limits.

OFFSET(1LSB) = VREF/(PGA_CHn x 1.5 x 8388608)

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