MCP3913 datasheet(19/82 Pages) MICROCHIP

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 2013 Microchip Technology Inc.

DS20005227A-page 19

MCP3913

3.7

Data Ready Output (DR)

The data ready pin indicates if a new conversion result

is ready to be read. The default state of this pin is logic

high when DR_HIZ = 1, and is high-impedance when

DR_HIZ = 0 (default). After each conversion is

finished, a logic low pulse will take place on the data

ready pin to indicate the conversion result is ready as

an interrupt. This pulse is synchronous with the master

clock and has a defined and constant width.

The data ready pin is independent of the SPI interface

and acts like an interrupt output. The data ready pin

state is not latched, and the pulse width (and period)

are both determined by the MCLK frequency,

over-sampling rate, and internal clock prescale

settings. The data ready pulse width is equal to half a

DMCLK period and the frequency of the pulses is equal

to DRCLK (see Figure 1-3).

3.8

Oscillator and Master Clock

Input Pin (OSC1/CLKI)

OSC1/CLKI and OSC2 provide the master clock for the

device. When CLKEXT = 0, a resonant crystal or clock

source with a similar sinusoidal waveform must be

placed across the OSC1 and OSC2 pins to ensure

proper operation.

The typical clock frequency specified is 4 MHz. For

proper operation, and for optimizing ADC accuracy,

AMCLK should be limited to the maximum frequency

defined in Table 5-2 for the function of the BOOST and

PGA setting chosen. MCLK can take larger values as

long as the prescaler settings (PRE<1:0>) limit

AMCLK = MCLK/PRESCALE in the defined range in

Table 5-2. Appropriate load capacitance should be

connected to these pins for proper operation.

3.9

Crystal Oscillator (OSC2)

When CLKEXT = 0 (default), a resonant crystal or

clock source with a similar sinusoidal waveform must

be placed across the OSC1 and OSC2 pins to ensure

proper operation. Appropriate load capacitance should

be connected to these pins for proper operation.

When CLKEXT = 1, this pin should be connected to

DGND at all times (an internal pull down operates this

function, if the pin is left floating).

3.10

Chip Select (CS)

This pin is the Serial Peripheral Interface (SPI) chip

select that enables serial communication. When this

pin is logic high, no communication can take place. A

chip select falling edge initiates serial communication,

and a chip select rising edge terminates the

communication. No communication can take place

even when CS is logic low, if RESET is also logic low.

This input is Schmitt-triggered.

3.11

Serial Data Clock (SCK)

This is the serial clock pin for SPI communication. Data

is clocked into the device on the rising edge of SCK.

Data is clocked out of the device on the falling edge of

SCK.

The MCP3913 SPI interface is compatible with SPI 0,0

and 1,1 modes. SPI modes can be changed during a

CS high time.

The maximum clock speed specified is 20 MHz. SCK

and MCLK are two different and asynchronous clocks;

SCK is only required when a communication happens,

while MCLK is continuously required when the part is

converting analog inputs.

This input is Schmitt-triggered.

3.12

Serial Data Output (SDO)

This is the SPI data output pin. Data is clocked out of

the device on the falling edge of SCK.

This pin remains in a high-impedance state during the

command byte. It also stays high-impedance during the

entire communication for write commands and when

the CS pin is logic high, or when the RESET pin is logic

low. This pin is active only when a read command is

processed. The interface is half-duplex (inputs and

outputs do not happen at the same time).

3.13

Serial Data Input (SDI)

This is the SPI data input pin. Data is clocked into the

device on the rising edge of SCK. When CS is logic low,

this pin is used to communicate with a series of 8-bit

commands. The interface is half-duplex (inputs and

outputs do not happen at the same time).

Each communication starts with a chip select falling

edge followed by an 8-bit command word, entered

through the SDI pin. Each command is either a Read or

a Write command. Toggling SDI after a Read command

or when CS is logic high has no effect.

This input is Schmitt-triggered.

Note:

This pin should not be left floating when

the DR_HIZ bit is low; a 100 k

 pull-up

resistor

connected

DVDD

recommended.

Note:

When CLKEXT = 1, the crystal oscillator

is disabled. OSC1 becomes the master

clock input CLKI, a direct path for an

external clock source. One example

would be a clock source generated by an

MCU.

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