MCP3913 datasheet(65/82 Pages) MICROCHIP

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 2013 Microchip Technology Inc.

DS20005227A-page 65

MCP3913

bit 14

EN_INT:

Enable for the CRCREG interrupt function

= The interrupt flag for the CRCREG checksum verification is enabled. The data ready pin (DR) will

become logic low and stays logic low if a CRCREG checksum error happens. This interrupt is

cleared if the LOCK<7:0> value is made equal to the PASSWORD value (0xA5).

= The interrupt flag for the CRCREG checksum verification is disabled. The CRCREG<15:0> bits are

still calculated properly and can still be read in this mode. No interrupt is generated even when a

CRCREG checksum error happens. (Default)

bit 13-12

Reserved:

Should be kept equal to 0 at all times

bit 11-6

Unimplemented:

Read as 0

bit 5-0

DRSTATUS<5:0>:

Data ready status bit for each individual ADC channel

DRSTATUS<n> = 1 - Channel CHn data is not ready (DEFAULT)

DRSTATUS<n> = 0 - Channel CHn data is ready. The status bit is set back to '1' after reading the

STATUSCOM register. The status bit is not set back to '1' by the read of the corresponding channel

ADC data.

STATUSCOM REGISTER (CONTINUED)

MCP3913 数据表(PDF) 65 Page - Microchip Technology