MT9072AB datasheet(108/275 Pages) ZARLINK

108 / 275 page

MT9072

Data Sheet

108

Zarlink Semiconductor Inc.

17.1.1.2

Binary Address

(A11-A0)

Hex

Address

Accessed

Processor

Access

ST-BUS

Access

yyyy 0000 xxxx

yyyy1111 xxxx

Y0X

YFX

Master Control

R/W

---

yyyy 0001 xxxx

Y1X

Master Status

---

yyyy 0010 xxxx

Y2X

Latched Status

---

yyyy 0011 xxxx

Y3X

Interrupt Status

---

yyyy 0100 xxxx

Y4X

Interrupt Mask

R/W

---

yyyy 0101 xxxx

yyyy 0110 xxxx

Y5X-Y6X

Per Channel Tx signaling

R/W

yes

yyyy 111 xxxx

yyyy 1000 xxxx

Y7X-Y8X

Per Channel Receive signaling

R/W

yes

yyyy 1001 xxxx

yyyy 1010 xxxx

Y9X-YAX

Per Channel Control

R/W

---

yyyy 1011 xxxx

yyyy 1100 xxxx

YBX-YCX

not used

yyyy 1101 xxxx

yyyy 1110 xxxx

YDX-YEX

not used

xxxx indicates all (0000 to 1111) binary possibilities

X indicates all (0 to F) hex possibilities

yyyy indicates 9 (000, 001, 010, 011, 111,1000,1001) binary possibilities representing 1 of 8 framers (R/W), and

all 8 framers (W only) and global selection.

Y indicates 9 (0,1,2,3,4...9) hex possibilities representing 1 of 8 framers (R/W), and all 8 framers (W only), and

global selection.

Table 56 - Register Group Address (Y00 - YFF) Summary (T1)

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